tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 296

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

SCL
SDA
<PIN>
INTS2 Interrupt
Request
(3) Transferring one word of data
one word of data, SBI0SR<MST> is tested to determine whether the device is placed in master mode
or slave mode.
Note: DMA transfer can be used only when the following conditions are satisfied:
2)
1)
During the INTS2 interrupt processing which takes place after the device has finished transferring
In transmitter mode (when SBI0SR<TRX> = 1)
Figure 3.12.12 Generating a Start Condition and Slave Address
Start condition
In slave mode
eight clock pulses on the SCL line after the start condition. The start condition is also received
from the master device. When a general call or an address identical to the slave address which
has been set in I2C0AR is received, the SDA line is pulled Low on the ninth clock pulse to
output an acknowledge signal.
SBI0CR2<PIN> to 0. In slave mode, the SCL line is held Low while PIN = 0.
In master mode (when SBI0SR<MST> = 1)
therefore, a sequence for generating a stop condition (described later) should be performed to
terminate the data transfer.
be transferred is 8 bits long, write the transfer data to SBI0DBR. If it is not 8 bits long, set
SBI0CR1<BC2:BC0> and SBI0CR1<ACK> before writing the transfer data to SBI0DBR.
When data is written to the data buffer register, SBI0CR2<PIN> is set to 1, the serial clock for
transferring the next word of data is generated from the input on the SCL pin, and one word of
data is output on the SDA pin. When the device has finished transferring data, an INTS2
interrupt request is generated, SBI0CR2<PIN> is reset to 0 and the SCL pin is pulled Low. To
transfer more than one word, repeat the above procedure starting from the test of
SBI0SR<LRB>.
In slave mode a start condition and slave address are received.
The slave address and the direction bit are received from the master device with the first
An INTS2 interrupt request is generated at the falling edge of the ninth clock pulse, resetting
SBI0SR<TRX> is tested to determine whether the device is a transmitter or a receiver.
SBI0SR<LRB> is tested. If SBI0SR<LRB> = 1, the receiver is not requesting data;
If SBI0SR<LRB> = 0, the receiver is requesting the next data item. If the next data item to
- A single master corresponds to a single slave.
- Continuous transmission or reception is possible.
A6
1
A5
2
TMP1942CY/CZ-295
A4
3
Slave address + direction bit
A3
4
A2
5
A1
6
A0
TMP1942CY/CZ
7
R/
W
8
Master output
Slave output
ACK
9
Ack from slave