tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 405

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

LWL and LWR Instructions
Problem:
The LWL or LWR instruction might provide incorrect results.
•
•
Note:
Workarounds:
To use the LWL or LWR instruction,
1) Place a NOP between a load instruction and the LWL or LWR instruction, or
2) Disable the data cache snooping of the DMAC before the LWL or LWR instruction is executed.
Problem-Causing Situation #1:
Problem-Causing Situation #2:
This problem occurs when all of these conditions are true.
This problem occurs when all of these conditions are true.
a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to
b. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will be
c. The DMAC is programmed for data cache snooping. Once the load instruction is executed, the
a. The destination of a load instruction (LB, LBU, LH, LHU, LW, LWL or LWR) is identical to
b. The Doze or Halt bit in the Config register is set to 1 immediately before the load instruction.
c. The instruction pipeline is full. (The load instruction and the LWL or LWR instruction will be
d. After the load instruction is executed, the processor is put in the STOP, SLEEP or IDLE mode.
e. After an interrupt signaling brings the processor out of the STOP, SLEEP or IDLE mode, the
Also, don’t put the processor in STOP, SLEEP or IDLE mode before the LWL or LWR
instruction is executed.
This applies to the case in which an interrupt signaling does not generate an interrupt
upon exit from STOP, SLEEP or IDLE mode. In other words, either the IEc bit in the
Status register is cleared (interrupts disabled), or if the IEc bit is set, the priority level of
the incoming interrupt signaling is lower than the mask level programmed in the CMask
field in the Status register. (Exit from STOP, SLEEP or IDLE mode can be accomplished
even with such settings.)
that of the LWL or LWR instruction.
executed consecutively.)
DMAC initiates a DMA transaction. After it has been serviced, the LWLor LWR instruction is
executed.
that of the LWL or LWR instruction.
executed consecutively.)
LWL or LWR instruction is executed.
TMP1942CY/CZ-404
TMP1942CY/CZ