tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 160

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

3.8.4.5
3.8.4.6
channel operation. There are two types of interrupts which can be requested in this case: normal
completion interrupt and abnormal completion interrupt.
Channel priority
Therefore, if transfer requests occur for channels 0 and 1 simultaneously, the DMAC will perform
the transfer operation for channel 0’ s transfer request first. When there are no more transfer requests
for channel 0, if the transfer request for channel 1 is still in effect, the DMAC will perform the
transfer operation on channel 1. (For internal transfer requests, the transfer request is held unless it is
cleared. For external transfer requests, this depends on the active state which has been set for the
interrupt request assigned to DMA requests by the interrupt controller. If the active state is set to
edge mode, the transfer request will be held by the interrupt controller. However, if the active state is
set to level mode, the interrupt controller will not hold the transfer request. Therefore, if level mode
is set, the interrupt request signal must be kept asserted until it is recognized by the DMAC.)
transition will occur. The data transfer on channel 1 will be suspended and the DMAC will start
transfer on channel 0. When there are no more transfer request for channel 0, the DMAC will
resumes the transfer operation on channel 1.
the unit of data transfer. In dual-address mode, this is when the DMAC has finished writing all the
stored data from the DHR register to the destination device.
Interrupts
The DMAC can generate an interrupt request to the TX19 processor core on completion of
The DMAC has four channels. A channel with a lower channel number always has higher priority.
If a transfer request for channel 0 occurs while data transfer on channel 1 is under way, a channel
Channel transition occurs when the DMAC has finished transferring an amount of data equal to
• Termination due to bus errors
• Normal completion interrupt
• Abnormal completion interrupt
-A value which cannot be divided by the unit of data transfer is set in the BCRn register.
-Values which cannot be divided by the unit of data transfer are set in the SARn and DARn
-An illegal combination of the device port size and data transfer unit has been set.
-The Str bit in the CCRn register is set to 1 while the BCRn register = 0.
-The CPU is notified that a bus error has occurred during data transfer.
register is set to 1 at the same time that the AbC bit in the CSRn register is set to 1.
At this time, if normal completion interrupts have been enabled using the NIEn bit in the
CCRn register, an interrupt request to the TX19 processor core is generated.
1. At this time, if abnormal completion interrupts have been enabled by the AbIEn bit in the
CCRn register, an interrupt request to the TX19 processor core is generated.
registers.
When transfer terminates abnormally due to a bus error, the BES or BED bit in the CSRn
When channel operation terminates normally, the NC bit in the CSRn register is set to 1.
When channel operation terminates abnormally, the AbC bit in the CSRn register is set to
TMP1942CY/CZ-159
TMP1942CY/CZ