tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 265

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(0xFFFF_F293)
SC5CR
Note 1: All error flags are cleared to 0 when read.
Note 2: For SCLK output operation, set SCLKS to 0 (rising edge).
Bit symbol
Read/Write
After reset
Function
Receive
data bit 8
Figure 3.11.25 Serial Control Register (SC5CR, for SIO5)
RB8
—
7
R
Parity type
0: Odd
1: Even
EVEN
6
0
R/W
TMP1942CY/CZ-264
Parity
0: Disabled
1: Enabled
PE
5
0
Overrun
OERR
R (cleared to 0 when read)
4
0
Parity/
underrun
1: Error
PERR
3
0
Framing error flag
Parity error/underrun error flag
Overrun error flag
I/O interface input clock selection
Active edge selection for SCLK0 input
Parity type
0
1
0
1
0
1
Framing
Baud rate generator
SCLK0 pin input
Data transmitted/received
at rising edge of SCLK0
Data transmitted/received
at falling edge of SCLK0
Odd parity
Even parity
FERR
2
0
TMP1942CY/CZ
0: SCLK0
1: SCLK0
SCLKS
1
0
R/W
0: Baud rate
1: SCLK0
generator
pin input
IOC
0
0
Cleared to
0 when
read