tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 69

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

*: Set this bit when using the pin for a STOP mode termination interrupt with SYSCR<DRVE> set to 0.
Pn: Port n Register, PnCR: Port n Control Register, PnFC: Port n Function Register
Note 1:
Note 2: When P50–P57 are configured as analog channels of the ADC, the ADCH[2:0] field in A/D Mode
Note 3: When P57 is configured as
Note 4: When PD6–PD7 are configured as XT1–XT2, the SYSCR0 register must be programmed to
Note 5: When PortD and PortE and PortF are configured as SDA and SCL outputs for the SBI, the
X: Don’t care
Otherwise, the bit need not be set.
Port D
Port E
Port F
Port
Control Register 1 (ADMOD1) is used to select a channel(s).
and disable the external trigger input to the ADC.
enable oscillation, etc.
ODEA[7:6] field in the Open-Drain Enable (ODE) register can be used to configure them as
either push-pull or open-drain ouptuts. Upon reset, the default is push-pull.
P4FC register bit is set and when the bus is released.
HWR
,
R
/
PD5
PD6
PD7
PE0~PE7
PE0
PE1
PE2
PE3
PE4
PE5
PE6
PE7
PF0~PF6
PF0
PF1
PF2
PF3
PF4
PF5
PF6
W
and
Pin Name
P40 to P43 have their internal pullup resistors enabled when the corresponding
Table 3.5.2 I/O Port Programmability (4/4)
CTS3
CTS4
CTS3
SCLK1(Input)
SCLK1(Output)
TABOUT
XT1
XT2
Input
Output
TXD3
RXD3
SCLK3(Input)
SCLK3(Output)
TXD4
RXD4
SCLK4(Input)
SCLK4(Output)
INT1
INT2
Input
Output
TXD5
RXD5
KEYD
SCLK5(Input)
SCLK5(Output)
CTS
SCK(Input)
SCK(Output)
SO
SDA
SI
SCL
INT0
ADTRG
Direction / Function
TMP1942CY/CZ-68
, the ADTRGE bit in the ADMOD1 register is used to enable
Pn
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
I/O Register Settings
PnCR
TMP1942CY/CZ
0
1
0
1
0
1
1
0
0
1
0
1
0
0
1
0
0
0
0
1
1
0
0
0
1
0
0
1
1
1
1
1
0
-
-
PnFC
1*
1*
1*
1
1
1
0
0
0
1
1
1
1
1
1
1
1
1
1
0
0
1
1
1
1
1
1
1
1
1
1
1
1
-
-
PnFC2
0
0
0
1
-
-