tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 272

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Timing at which transmit
data is written to buffer
SCLK0 output
TXD0
(INTTX0 interrupt request)
TBRUN
Timing at which transmit
data is written to buffer
SCLK0 output
TXD0
(INTTX0 interrupt request)
TBRUN
TBEMP
Timing at which transmit
data is written to buffer
SCLK0 output
TXD0
(INTTX0 interrupt request)
TBRUN
TBEMP
3.11
11
3.11.4
3.11.4
Functional description for each mode
Functional description for each mode
(1) Mode 0 (I/O interface mode)
(1) Mode 0 (I/O interface mode)
Figure 3.11.36 Transmit Operation in I/O Interface Mode (SCLK0 Output Mode)
Figure 3.11.36 Transmit Operation in I/O Interface Mode (SCLK0 Output Mode)
SCLK is generated internally by the device, and SCLK input mode, in which the synchronizing
SCLK is generated internally by the device, and SCLK input mode, in which the synchronizing
clock SCLK is input from an external source.
clock SCLK is input from an external source.
1)
1)
This mode comprises two submodes: SCLK output mode, in which the synchronizing clock
This mode comprises two submodes: SCLK output mode, in which the synchronizing clock
Transmission
Transmission
data and the synchronizing clock signal are output on the TXD0 and SCLK0 pins, respectively,
data and the synchronizing clock signal are output on the TXD0 and SCLK0 pins, respectively,
each time the CPU writes data to the transmit buffer. When all the data bits have been output,
each time the CPU writes data to the transmit buffer. When all the data bits have been output,
an INTTX0 interrupt is generated.
an INTTX0 interrupt is generated.
buffer 2 to transmit buffer 1 when the CPU writes data to transmit buffer 2 while transmission
buffer 2 to transmit buffer 1 when the CPU writes data to transmit buffer 2 while transmission
is stopped or when data has been transmitted from transmit buffer 1 (shift register).
is stopped or when data has been transmitted from transmit buffer 1 (shift register).
Simultaneously, SC0MOD2<TBEMP> is set to 1 and an INTTX0 interrupt occurs. If transmit
Simultaneously, SC0MOD2<TBEMP> is set to 1 and an INTTX0 interrupt occurs. If transmit
buffer 2 does not contain data to be transferred to transmit buffer 1, SCLK0 output is stopped
buffer 2 does not contain data to be transferred to transmit buffer 1, SCLK0 output is stopped
without generating an INTTX0 interrupt.
without generating an INTTX0 interrupt.
If WBUF = 0, that is, the transmit double-buffer is disabled in SCLK output mode, 8 bits of
If WBUF = 0, that is, the transmit double-buffer is disabled in SCLK output mode, 8 bits of
If WBUF = 1, that is, the transmit double-buffer is enabled, data is transferred from transmit
If WBUF = 1, that is, the transmit double-buffer is enabled, data is transferred from transmit
When WBUF = 1 (if buffer 2 does not contain data)
When WBUF = 1 (if buffer 2 contains data)
bit 0
bit 0
bit 0
TMP1942CY/CZ-271
When WBUF = 0
bit 1
bit 1
bit 1
bit 6
bit 6
bit 6
TMP1942CY/CZ
bit 7
bit 7
bit 7
bit 0
bit 0