tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 293

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

Master A
Master B
(11) Monitoring detection of a slave address match
(12) Monitoring detection of a general call
(13) Monitoring the last bit received
the rising edge of the SCL clock. If the levels do not match, it is assumed that arbitration is lost and
SBI0SR<AL> will be set to 1.
receiver mode. SBI0SR<AL> is cleared to 0 by writing data to or reading data from SBI0DBR, or by
writing data to SBI0CR2.
receives a general call or a slave address of the same value as that set in I2C0AR, SBI0SR<AAS>
will be set to 1. If I2C0AR<ALS> = 1, SBI0SR<AAS> will be set to 1 upon the reception of the first
word. The AAS flag is cleared to 0 by writing data to or reading data from SBI0DBR.
start condition are all 0) in slave mode, and is reset to 0 when a start or stop condition is detected on
the bus.
clock. In acknowledgment mode, the value read from SBI0SR<LRB> immediately after an INTS2
interrupt request has been generated is equivalent to the value of the ACK signal.
Internal SCL
Output
Internal SDA
Output
Internal SCL
Output
Internal SDA
Output
<AL>
<MST>
<TRX>
Access to SBI0DBR or
SBI0CR2
The internal SDA output level for each master is compared with the level of the bus SDA line at
At this point the SBI0SR<MST,TRX> bits are reset to 00, thus placing the master into slave
If the device is operating as a slave device in address recognition mode (I2C0AR<ALS> = 0) and
SBI0SR<AD0> is set to 1 when a general call is received (i.e. when the eight data bits after the
SBI0SR<LRB> holds the value of the SDA line which is latched at the rising edge of the SCL
Figure 3.12.11 Example for Master B (D7A = D7B, D6A = D6B)
D7A
D7B
1
1
D6A
D6B
TMP1942CY/CZ-292
2
2
D5A
3
3
D4A
4
4
D3A
Internal SDA output
Internal SCL output
5
Clock output stops here.
D2A
6
D1A
7
D0A
8
TMP1942CY/CZ
9
D7A’ D6A’ D5A’ D4A’
1
2
3
4