tmp19a43fzxbg TOSHIBA Semiconductor CORPORATION, tmp19a43fzxbg Datasheet - Page 168

• Manufacturer Part Number: tmp19a43fzxbg
• Description: 32bit Tx System Risc
• Manufacturer: TOSHIBA Semiconductor CORPORATION

(2) Up-counters (UC0 and UC1)
(3) Timer registers (TA0REG and TA1REG)
selected in timer mode register TA01MOD.
prescaler output clocks, φT1, φT4 or φT16, according to the value set in TA01MOD <TA0CLK1:
TA0CLK0>.
overflow output is the input clock for UC1; in any other mode, the input clock for UC1 is either one
of the three prescaler output clocks, φT1, φT16 or φT256, or the comparator output (match detection)
from TMRA0, as determined by the value set in TA01MOD<TA1CLK1:TA1CLK0>.
the up-counters are cleared with the timers stopped.
these timer registers matches the corresponding up-counter value, the comparator’s match detection
signal becomes active. If the value set is 00H, this signal will become active when the up-counter
overflows.
controlled by the setting of TA01RUN<TA0RDE>. The double-buffer is disabled when <TA0RDE>
= 0 and enabled when <TA0RDE> = 1.
initiated by a 2
double-buffer cannot be used in timer mode.
write data in the timer register and set <TA0RDE> to 1, then write the following data in the register
buffer.
UC0 and UC1 are 8-bit binary counters which count up synchronously with the input clock
The input clock for UC0 is either the external clock entered via the TA0IN pin or one of the three
The input clock for UC1 varies with the operating mode. In 16-bit timer mode, up-counter UC0’s
The TA01RUN<TA0RUN> and <TA1RUN> bits set the up-counters to run or stop. When reset,
TA0REG and TA1REG are 8-bit registers used to set interval times. When the value set in one of
TA0REG is paired with a register buffer to form a dual-buffer structure. The double-buffer is
When the double-buffer is enabled, data transfer from the register buffer to the timer register is
When reset, <TA0RDE> is initialized to 0, disabling the double-buffer. To use the double-buffer,
Figure 3.9.2 shows the structure of TA0REG.
n
-1 overflow in PWM mode or by cycle match detection in PPG mode. The
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