PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 90

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
5. TM3260 VLIW Media Processor Core
PNX15XX_PNX952X_SER_N_4
Product data sheet
PNX15xx/952x Series provides 5 chip selects for the XIO bus. The TM3260 can
execute or read from direct addressable Flash types. Execution from Flash is low
performance, and only recommended for boot usage. After boot, it is recommended
that code files be transferred from Flash to DRAM where they can be executed more
efficiently. Flash cannot be the target of a module DMA write, because write
operations require a software flash programming protocol.
Execution and direct addressed read operations only apply to addressable Flash
types, such as traditional Flash, and not to the “file system like” NAND Flash type.
Peak page mode read performance is 66 MB/s for 16-bit devices and 33 MB/s for 8-
bit devices such as the configurable x8/x16 Intel StrataFlash (28FxxxJ3A, 32Mbits,
64Mbits, 128Mbits) and ST MLC-NOR flash (M58LW064A, 64Mbits). Cross-page
random read accesses each take 4 to 5 PCI clock cycles depending on the access-
time of the device.
Flash is mostly used during system boot or low bandwidth system operation to
provide a small, non-volatile file system.
The TM3260 CPU is a version of the TriMedia 32-bit VLIW media processor. This
Very Long Instruction Word (VLIW) processor operates at up to 300 MHz with 5
instructions per clock cycle, and provides an extensive set of multimedia instructions.
It implements the TriMedia PNX1300 Series instruction set, and has a superset of the
PNX1300 Series functional units as well as a superset of the multimedia instruction
set for better fit with MPEG-4 advanced profile decoding. It is backwards compatible
with PNX1300 Series CPU, but has a larger Instruction cache (also referred as I$ or
Icache) for improved performance. In addition, re-compilation of source code results
in higher media performance due to the additional functional units.
The TM3260 supports 32-bit integer and IEEE compatible 32-bit floating point data
formats. It also provides a Single Instruction Multiple Data (SIMD) style operation set
for operating on dual 16-bit or quad 8-bit packed data.
The TM3260 has sufficient compute performance to deal with a variety of future
operating modes. By itself, the processor can decode any known compressed video
stream and associated audio at full frame rate, such as decoding a DV camcorder
image stream, MPEG-2 or MPEG-4 decode. The processor is also capable of doing
all audio and video compression, decompression and processing necessary for bi-
directional video conferencing.
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At 266 MHz it has a peak floating point compute capacity of 1.0 Goperations/s,
and has 1.3 Gmultiply-add/s capability on 16-bit data. Its dual access 16 KB 8-
way set-associative data cache provides a CPU local data bandwidth of 2.0 GB/s.
Its 64 KB 8-way set-associative instruction cache provides 224 bits of instructions
every clock cycle (7.1 GB/s), for an instruction rate of 8.8 Gop/s.
At 300 MHz it has a peak floating point compute capacity of 1.4 Goperations/s,
and has 1.5 Gmultiply-add/s capability on 16-bit data. Its dual access 16 KB 8-
way set-associative data cache provides a CPU local data bandwidth of 2.3 GB/s.
Its 64 KB 8-way set-associative instruction cache provides 224 bits of instructions
every clock cycle (8.0 GB/s), for an instruction rate of 9.9 GB/s.
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 2: Overview
© NXP B.V. 2007. All rights reserved.
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