PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 325

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.4 Clock Programming
2.5 Power Management
Some Examples
If RANK0_ADDR_LO is set to 0x0800:0000, RANK0_ADDR_HI to 0x0bff:ffff, and
RANK1_ADDR_HI to 0x0dff:ffff. This implies a 64-MB rank 0 starting at address
0x0800:0000, and a 32 MB rank 1 starting at address 0x0c00:0000.
If the address 0x0900:0000 has to be mapped, the upper 4 bits of the 32-bit address
are ignored. The address is located at byte offset 0x0100:0000 in rank 0.
If the address 0x3900:0000 has to be mapped, the upper 4 bits of the 32-bit address
are ignored. The address is located at byte offset 0x0100:0000 in rank 0.
If the address 0x0c80:0000 has to be mapped, the upper 4 bits of the 32-bit address
are ignored. The address is located at byte offset 0x0080:0000 in rank 1.
If the address 0x3c80:0000 has to be mapped, the upper 4 bits of the 32-bit address
are ignored. The address is located at byte offset 0x0080:0000 in rank 1.
If the address 0x0500:0000 has to be mapped, the upper 4 bits of the 32-bit address
are ignored. The address is not located within any of the two ranks, therefor an error
flag is set in MMIO register ERR_VALID to indicate this. Furthermore, the DDR
SDRAM Controller output signal “ip_2031_ddr_addr_err” is made ‘1’. The 28 lower
bits of the address indicate a reference below rank 0. Therefor, this address is aliased
to rank 0. The aliased address is located at byte offset 0x0100:0000 in rank 0.
If the address 0x0e80:0000 has to be mapped, the upper 4 bits of the 32-bit address
are ignored. The address is not located within any of the two ranks, therefore an error
flag is set in MMIO register ERR_VALID to indicate this. Furthermore, the IP_2031
output signal “ip_2031_ddr_addr_err” is made ‘1’. The 28 lower bits of the address
indicate a reference above rank 1. Therefore, this address is aliased to rank 1 and
located at byte offset 0x0080:0000 in rank 1.
The DDR clock is managed by the Clock module. Both clk_mem and clk_dtl_mmio
must be on.
In order to reduce power consumption, the DDR SDRAM Controller can be turned
into halt mode. During halt mode, the clock inputs to the DDR controller may be
turned off to reduce dynamic power consumption. When the clock inputs to the DDR
controller are turned off, it will be non-functional. The DDR controller assumes that
during halt mode the clock inputs to the DLLs may be turned off as well. As a result,
the DDR controller power up sequence includes resetting the DLLs.
Note that when the clock inputs to the DDR controller are turned off, no access to the
DDR controller MMIO registers is possible.
Putting the DDR SDRAM Controller in halt mode, and keeping the clock inputs to the
DDR controller turned on, allows for safe programming of the MMIO registers using
the DTL MMIO interface. When MMIO registers DDR_MR and DDR_EMR are re-
programmed, a start action has to be performed (after the DDR controller is
unhalted), for the new DDR values to take effect.
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
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