PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 434

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 3: Video Input Formats
PNX15XX_PNX952X_SER_N_4
Product data sheet
Video Modes
D1
VMI
RAW
HD
8-bit
10-bit
8-bit
10-bit
8-bit
10-bit
8-bit
10-bit
Single Stream (YUV)
Embedded Sync
X
X
where the synchronization reference is provided explicitly via HREF, VREF, and FREF
signals (as specified in the implementation of the TDA9975(A) decoder from NXP and
the HMP8117 decoder from Intersil). In HD mode HREF, VREF, and FREF are
respectively connected to the VIP module pins hrefhd, vrefhd an frefhd. The
supported mode is shown in
this HD mode, the code is expected to be in the U/V stream; to this end, the current
design checks only one of the streams, the U/V stream, for the presence of the
embedded codes, assuming that any information embedded in the Y stream is
identical (see ITU BT 1120, SMPTE 274M standards). The DUAL_STREAM register
must be programmed to 1 in this mode.
Remark: The explicit sync signals are used only in the HD or DUAL_STREAM mode.
Table 3
input formats, where an X designates the presence (support) of the corresponding
feature.
Figure 6:
tries to capture the above discussion into a quick checklist of implemented
HD Dual Data Stream
Rev. 4.0 — 03 December 2007
Explicit Sync No Sync Embedded Sync
X
Channel B
Channel A
Figure
X
X
6. Note that for detecting the embedded sync in
FF
FF
EAV/SAV
Identical
00
00
00
00
Dual Stream (Y and U/V)
X
X
XY
XY
Y
U
Chapter 12: Video Input Processor
Y
V
PNX15xx/952x Series
U
Y
Y Y Y
V U V
Explicit Sync No Sync
X
X
© NXP B.V. 2007. All rights reserved.
X
X
12-434