PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 492

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.7.4 MBE Interrupt
2.7.5 OVERFLOW Interrupt (Message Passing Mode Only)
2.8 Record or Message Counters
2.9 Timestamp
Capture continues upon receipt of either BUF1FULL_ACK or BUF2FULL_ACK or
both. Refer to
OVERRUN condition is ‘sticky’ and can only be cleared by software writing a ‘1’ to the
FGPI_IR_CLR.OVERRUN_ACK bit.
A Memory Bandwidth Error (MBE) interrupt is generated when received samples can
not be loaded into the main memory adapter FIFO. One or more data samples will be
lost until the adapter FIFO can accept samples. Sample capture resumes at the
correct address.
The MBE condition is ‘sticky’ and can only be cleared by software writing a ‘1’ to the
FGPI_IR_CLR.MBE_ACK bit.
If the message length overflows the value programmed in the FGPI_REC_SIZE
register, the message is truncated and the FGPI_IR_STATUS.OVERFLOW interrupt
will be generated.
The OVERFLOW condition is ‘sticky’ and can only be cleared by software writing a ‘1’
to the FGPI_IR_CLR.OVERFLOW_ACK bit.
The registers FGPI_NREC1 and FGPI_NREC2 count the number of complete
records or messages transferred to memory. The counters are incremented when a
record or message stop event is seen. The counters are cleared to zero when the
associated FGPI_BASEn register is updated.
Reading a FGPI_NRECn register while the associated buffer is active MAY NOT
RETURN THE ACTUAL TRANSFER COUNT (can be less than or equal to the actual
count) due to clock domain crossing logic. The best time to read a FGPI_NRECn
register is during the associated BUFnFULL interrupt service routine as the counter is
not updated during this time.
See
information on how to use FGPI_NRECn while the associated buffer is active.
If enabled, by setting FGPI_CTL.TSTAMP_SELECT bit to ‘1’, a 4-byte time-of-arrival
word giving the record or message start event time is written to main memory before
sample data.
The timestamp clock is derived from the main timestamp clock which runs at 13.5
MHz when the GPIO module module is clocked by the 108 MHz clock.
–
–
–
–
Section 2.7.2 THRESH1_REACHED and THRESH2_REACHED Interrupts
a buffer full event has occurred and
the buffer full interrupt has not been acknowledged and
the corresponding enable bit is set and
a new record or message start event has arrived
Figure 4 on page 14-494
Rev. 4.0 — 03 December 2007
Chapter 14: FGPI: Fast General Purpose Interface
to see which buffer capture resumes in. The
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
14-492
for