PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 343

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 9: Register Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
15:0
1
2
Offset 0x06 51C4
31:8
7:0
Offset 0x06 51C8
31:16
15:0
Offset 0x06 51CC
31:8
7:0
Performance Measurement
To allow for performance evaluation, the DDR SDRAM Controller includes a set of registers that measures data traffic.
Incremental 32-bit counters are used to measure the read and write traffic on every MTL port separately.
Offset 0x06 5200
31:0
Offset 0x06 5204
31:0
Offset 0x06 5208
31:0
Offset 0x06 520C
31:0
Offset 0x06 5240
31:0
Errors
These registers can be used to observe DDR memory addressing errors. If an MTL command is referring to an address
outside the DDR addressable region, the MTL command specifics are registered in the error registers, and an interrupt to the
TM3260 is raised to indicate the error. In the case of multiple successive errors, the MTL command that caused the first error
is registered, but successive errors are not registered (until the VALID field of ERR_VALID is set to ‘0’).
Offset 0x06 5280
31:1
When transferring a burst of n 32-bit data elements at a double data rate, the burst size in terms of clock cycles is n/2.
See register ARB_CPU_RATIO for a description of the RATIO value.
Symbol
LIMIT
Unused
RATIO
Reserved
CLIP
Reserved
DECR
MTL_RD_VALID
MTL_WR_ACCEPT
MTL_RD_VALID
MTL_WR_ACCEPT
IDLE
Unused
ARB_CPU_RATIO
ARB_CPU_CLIP
ARB_CPU_DECR
PF_MTL0_RD_VALID
PF_MTL0_WR_ACCEPT
PF_MTL1_RD_VALID
PF_MTL1_WR_ACCEPT
PF_IDLE
ERR_VALID
Access Value
R/W
R
R/W
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R
0xFFFF
-
0x04
-
0xFFFF
-
0x01
-
-
-
-
-
-
Rev. 4.0 — 03 December 2007
Description
When the DDR controller internal CPU account exceeds this value,
no CPU DDR burst will be performed when DMA traffic is present
(CPU traffic has lower priority than DMA traffic). The internal CPU
account is decremented by DECR every clock cycle. For increment
information see DYN_RATIOS description.
These bits should be ignored when read, and written as 0s.
If DYN_RATIOS are disabled the value is added to the internal
account for each CPU DDR burst. If DYN_RATIOS are enabled then
this value is added to the internal account for each clock cycle spent
on a CPU DDR burst.
These bits should be ignored when read, and written as 0s.
CPU account clip. When the internal account goes above this value
the CPU DDR bursts are ‘for free’. This value should always be
equal or higher than LIMIT.
These bits should be ignored when read, and written as 0s.
CPU account decrement. This value is used to decrement the
internal account of each clock cycle (with some exceptions).
Counter for valid MTL read data elements.
Counter for valid MTL write data elements.
Counter for valid MTL read data elements.
Counter for valid MTL write data elements.
Counts cycles in which the DDR memory controller is considered to
be idle (not valid entries on the top of the DDR arbitration queue).
These bits should be ignored when read, and written as 0s.
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
9-343