PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 252
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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Table 8: Registers Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
2:1
0
Offset 0x04 081C
This register sets up the profile of the XIO select 2 line. All times are in reference to PCI clocks.
31:25
24
23
22
21:18
17:14
13:9
8:5
4:3
2:1
0
Symbol
sel1_siz
en_sel1
Reserved
misc_ctrl
en_16bit_xio
sel2_use_ack
sel2_we_hi
sel2_we_lo
sel2_wait
sel2_offset
sel2_type
sel2_siz
en_sel2
XIO Sel2 Profile
Acces
s
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
Value
0
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
Amount of address space allocated to Sel1:
00 = 8M
01 = 16M
10 = 32M
11 = 64M
Enable sel1 profile.
68360: 1 synchronous DSACK; 0 asynchronous DSACK.
NOR: Not used
NAND: Not used
IDE: Not used
0 = 8 bit XIO device
1 = 16 bit XIO device
0 = Fixed wait state.
1 = Wait for ACK
Not used for IDE
68360: DS time high.
NOR: WN time high
NAND: REN profile, [19:18] low time; [21:20] high time
IDE: DIOR and DIOW high time
63860: Not used.
NOR: WN time low
NAND: WEN profile, [15:14] low time; [17:16] high time
IDE: DIOR and DIOW low time
68360: DS time low if using fixed timing.
NOR: OEN time low if not using ACK.
NAND: Delay between address and data phase if not using ACK,
delay until monitoring ACK.
IDE: Not used.
Address offset form start address of XIO aperture, in 8M
increments. This field must be naturally aligned with the size of the
profile.
Sel2 is configured as:
Amount of address space allocated to Sel2:
Enable sel2 profile.
00 = 68360 type device
01 = NOR Flash
10 = NAND-Flash
11 = IDE
00 = 8M
01 = 16M
10 = 32M
11 = 64M
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
7-252
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