PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 486

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 2:
fgpi_d_valid
fgpi_data
fgpi_start
fgpi_stop
FGPI Module Block Diagram
8/16/32
DTL
MMIO
I/F
1.2 VDI to FGPI pin mapping
1.3 DTL MMIO Interface
1.4 Data Packer
Refer to
VDI_D[32] maps to fgpi_start (fgpi_rec_start)
VDI_D[33] maps to fgpi_stop (fgpi_buf_start)
VDI_V2 maps to fgpi_d_valid
VDI_C2 maps to clock module fgpi_clk input
VDI_D[31:0] mapping depends on the VDI_MODE (Input Router) register settings as
described in the
This block contains all of the programmable registers used by the FGPI module
accessed through the MMIO bus. Refer to
descriptions. This block also handles clock domain crossing between the MMIO bus
clock and the FGPI module clock.
This block is used to pack incoming data samples into 32-bit words to be sent to main
memory. This module also informs the DMA Engine when a valid 32-bit data word is
ready to be loaded into the MTL DTL adapters FIFO via the DTL Initiators.
DATA
PACKER
BUFFER
SYNC
Figure
2. This block diagram shows the basic sections of the FGPI module.
Rev. 4.0 — 03 December 2007
Chapter 3 System On Chip
32
TIMESTAMP
LENGTH
DMA
ENGINE
Chapter 14: FGPI: Fast General Purpose Interface
32
32
Section 4. on page 14-501
Resources.
PNX15xx/952x Series
DTL
INITIATOR
DTL
INITIATOR
© NXP B.V. 2007. All rights reserved.
for register
14-486