PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 186

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 11: CLOCK MODULE REGISTERS
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x04,701C
31
30:0
Offset 0x04,7020
31
30:0
Offset 0x04,7024
31
30:0
Offset 0x04,7028
31
30:0
Offset 0x04,702C
31
30:0
Offset 0x04,7030
31
30:0
Divider Registers:
Offset 0x04,7034
31:8
8
7
6
5
4
3
2
Symbol
Enable
dds3_ctl[30:0]
Enable
dds4_ctl[30:0]
Enable
dds5_ctl[30:0]
Enable
dds6_ctl[30:0]
Enable
dds7_ctl[30:0]
Enable
dds8_ctl[30:0]
Reserved
pd_192
pd_173
pd_157
pd_144
pd_133
pd_123
pd_115
For register 34h power down appropriate clocks before setting these bits
DDS3_CTL
DD4_CTL
DDS5_CTL
DDS6_CTL
DDS7_CTL
DDS8_CTL
CAB_DIVIDER_CTL
Acces
s
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
…Continued
Value
0
0x02F68
4C0
0
0x02F68
4C0
0
0x00E90
452
0
0x04000
000
0
0x04000
000
0
0x04000
000
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS3 control (default = 20 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS4 control (default = 20 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS5 control (default = 128*48kHz = 6.14 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS6 control (default = 27 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS7 control (default = 27 MHz)
1: Enables the DDS. The input of the DDS is then the 1.7GHz clock.
0: Test mode. Do not use.
31-bit DDS8 control (default = 27 MHz)
To ensure software backward compatibility unused or reserved bits
must be written as zeros and ignored upon read.
Power down 192 MHz divider in the CAB block.
Power down 173 MHz divider in the CAB block.
Power down 157 MHz divider in the CAB block.
Power down 144 MHz divider in the CAB block.
Power down 133 MHz divider in the CAB block.
Power down 123 MHz divider in the CAB block.
Power down 115 MHz divider in the CAB block.
PNX15xx/952x Series
Chapter 5: The Clock Module
© NXP B.V. 2007. All rights reserved.
5-186