PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 804

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
3. Endian Mode Theory
PNX15XX_PNX952X_SER_N_4
Product data sheet
3.1 Law 1: The “CPU Rule”
There are two basic laws of endian mode: one imposed by CPU history, and one by
convention. Both must be met by any system architecture that implements dual-
endian operation capability. In addition, there are some implementation choices for a
system architecture.
PNX15xx/952x Series on-chip buses. These choices are somewhat arbitrary, but they
must be followed to ensure future compatibility.
This section is intended to explain CPU endian modes in detail. For those familiar
with CPUs and endian modes, it is optional reading.
The following summarizes how CPUs and byte-addressable memory operate:
Consider the following example a (hypothetical) C struct:
} DMA_Descriptor;
Remark: This is based on an example in the Apple
Cards and Drivers for Power Macintosh Computers,” Appendix A.
A compiler would assign byte offsets as follows: C:0, F:1, L:2, A:4. This assignment is
independent of system endian mode.
Figure 2
Figure 2:
•
•
•
When storing an “n byte” size item from a CPU register to memory at address “A,”
the bytes modified are always the bytes with byte address “A”..”A+n-1.”
In little-endian mode, the byte at address “A” receives the least significant bits of
the multi-byte item.
In big-endian mode, the byte at address “A” receives the most significant bits.
struct {
UInt8C;//"command" byte
UInt8F;//"flags" byte
UInt16L;//"length" 16 bit value
UInt32A;//"address" 32 bit value
and
0
Big-Endian Layout of DMA_Descriptor
C
Figure 3
Rev. 4.0 — 03 December 2007
1
Section 6.
F
show the two layout views.
Word 1
2
explains the choices that were made for the
L
4
PNX15xx/952x Series
Word 2
publication, ”Designing PCI
Chapter 29: Endian Mode
A
© NXP B.V. 2007. All rights reserved.
29-804