PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 658

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
3.3.1 VLD Input
3.3.2 VLD Output
Under normal circumstances, the CPU is interrupted whenever the VLD halts.
Consider the case in which the VLD has encountered a start code. At this point, the
VLD will halt and set the status flag which indicates that a start code has been
detected. This flag will generate an interrupt to the CPU. Upon entering the interrupt
service routine, the CPU will read the VLD status register to determine the source of
the interrupt. Once it has been determined that a start code has been encountered,
the CPU will read 8 bits from the VLD shift register to determine the type of start code
that has been encountered. If a slice start code has been encountered, the CPU will
read from the shift register the slice quantization scale code and any extra slice
information (from the slice header). The slice quantization scale code will then be
written back to the VLD_QS register. Before exiting the interrupt service routine, the
CPU will clear the start code detected status bit in the status register and issue a new
command to process the remaining macroblocks.
The VLD reads the video bitstream from the main memory and performs the variable
length decoding process. The CPU writes the main memory buffer address from
which bitstream to be read by VLD in VLD_INP_ADR register. The number of bytes to
be read by the VLD is updated by the CPU in the VLD_INP_CNT register.
The VLD unit uses two 64-byte buffers to store the input bitstream. The VLD reads
the bitstream data from the main memory and updates the VLD_INP_ADR and the
VLD_INP_CNT register. The content of the VLD_INP_ADR register reflects the next
fetch address of the bitstream data. The content of the VLD_INP_CNT register
reflects the number of bytes to be read from the main memory. When the number of
bytes to be read from the main memory transitions from non-zero to zero, the
DMA_INPUT_DONE flag in the VLD_MC_STATUS is set. An interrupt will be sent to
the CPU also if the corresponding interrupt enable bit in the VLD_IE register is set.
The CPU should then provide the new bitstream buffer address and the number of
bytes in the bitstream buffer to the VLD.
The VLD unit also updates a bit counter in the VLD_BIT_CNT register to keep track of
the number of bits consumed in the decoding process. The bit counter is updated
only after a successful decoding of a symbol. The CPU can read this bit counter from
the VLD_BIT_CNT register. This register can be initialized to zero by sending the
‘Initialize VLD’ command.
The output of the VLD are always transferred back to main memory for down stream
software MPEG blocks. All VLD output are transferred via DMA to separate main
memory areas for MB headers and run-level encoded DCT coefficients.
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The command was completed with no exceptions.
A start code was detected.
An error was encountered in the bitstream.
The VLD input DMA completed and the VLD is stalled waiting for more data.
One of the output DMA for RL or HDR processing has been completed.
Rev. 4.0 — 03 December 2007
Chapter 21: MPEG-1 and MPEG-2 Variable Length Decoder
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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