PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 330

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
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PNX15XX_PNX952X_SER_N_4
Product data sheet
3.4 Data Coherency
3.5 Programming the Internal Arbiter
any other MTL transactions pending in the DDR controller). When the read was to an
already activated row, in cycle 3 a DDR read command will appear on the DDR
interface. Given a CAS latency of n cycles (typically the CAS latency is 2, 2.5, 3, 3.5,
or 4 cycles), the first read data element will be presented by the memory device in
cycle 3 + n. To allow for safe clock domain transfer (from the “dqs” clock domain to the
“clk_mtl” clock domain) and to combine two DDR read data elements into a single
MTL read data element, the DDR controller takes two extra cycles before presenting
the read data on the MTL interface in cycle 3 + n + 2. As a result, the lowest latency
from MTL read command accept to first MTL read data element valid on the MTL
interface is 3 +
n + 2 cycles. In case of pending MTL transactions in the DDR controller, and in case
of required DDR precharge and activate commands, the latency will increase.
Memory requests at an MTL port of the DDR controller are processed and executed
in the order that they are received. The DDR controller does not re-order the
commands on a MTL interface. From this point of view data coherency between
memory bus agents that connect to a single port on the DDR controller is
guaranteed.
However, the memory requests that are made to different MTL interfaces on the DDR
SDRAM Controller in general will not be serviced in the order that they appeared. The
order in which these requests are serviced depends on the state of the DDR SDRAM
device(s) and how the internal arbiter is programmed. The user needs to take care of
data coherency between memory agents that connect to different MTL ports of the
DDR controller.
The window is defined by a 16-bit value that represents the size of the window in
terms of IP_2031 memory clock cycles. By choosing a certain ratio between the
HRT_WINDOW and the CPU_WINDOW, the available DDR bandwidth can be
divided between DMA traffic on MTL port 0, and CPU traffic on MTL port 1. The
window size may affect the latency of traffic. By choosing a large value for
HRT_WINDOW, the CPU traffic may get a large latency. However, for small window
sizes the DDR controller may not be able to divide the available DDR bandwidth
between DMA traffic and CPU traffic as expected by the programmed window sizes.
Window sizes between values 20 and 100 are advised to ensure acceptable traffic
latencies and proper dividing of available DDR bandwidth. E.g. to achieve a DDR
bandwidth division of 25% CPU traffic and 75% DMA traffic, a CPU_WINDOW of 25,
and a HRT_WINDOW of 75 could be programmed. Using a CPU_WINDOW of 100,
and a HRT_WINDOW of 300 would probably be able to achieve a more accurate
division of the bandwidth, but may result in unacceptable traffic latencies.
To program the parameters for the internal arbiter, follow the steps below:
1) Determine the total available bandwidth (tot_bw), based on the board DDR setup
(frequency and bus width). Note a Mega in Hz is not a M in Bytes! Use an average
DDR efficiency of 73%, determine required peak hard real time bandwidth (hrt_pk),
average hard real time bandwidth (hrt_avg), average soft real time (srt) and average
total CPU bandwidth (CPU).
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
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