PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 38

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 4: PNX1500 Interface
PNX15XX_PNX952X_SER_N_4
Product data sheet
Pin Name
AI_WS
AI_SD3
AI_SD2
AI_SD1
AI_SD0
Octal Audio Out (audio out always acts as sender, but can be set as master or slave for D/A timing)
AO_OSCLK
AO_SCK
BGA
Ball
AD21
AD22
AC17
AE23
AD19
AE18
AF24
Pad
Type
BPT3MCHDT5V
BPT3MCHDT5V
BPT3MCHDT5V
BPT3MCHDT5V
BPX2T14MCP
BPX2T14MCP
BPTS3CHP
Rev. 4.0 — 03 December 2007
I/O
Type
OUT
I/O
I/O
IN
IN
IN
IN
GPIO
#
16
20
19
18
17
-
-
P Description
U AI can operate in either master or slave mode.
D
D
D
D
U Over Sampling Clock. This output can be
U AO can operate in either master or slave mode.
AI_WS is the word-select or frame-synchronization
signal from/to the external A/D subsystem.
Serial Data from external A/D subsystem. Data on
this pin are sampled on positive or negative edge of
AI_SCK as determined by the CLOCK_EDGE bit in
the AI_SERIAL register. These pins are 5 V tolerant
input.
programmed to emit any frequency up to 50 MHz,
with a sub one Hertz resolution. It is intended to be
used as the 256 or 384 f
the external D/A conversion subsystem. A board
level 27-33
reduce ringing.
AO_SCK is limited to 25 MHz. The sample rate of
the valid samples is variable. If used as an output, a
board level 27-33
recommended to reduce ringing.
• When Audio In is programmed as the serial-
• When Audio In is programmed as the serial-
• When Audio Out is programmed to act as the
• When Audio Out is programmed to act as serial
interface timing slave (power-up default), AI_WS
acts as an input. AI_WS is sampled on the same
edge as selected for AI_SD[3:0].
interface timing master, AI_WS acts as an
output. It is asserted on the opposite edge of the
AI_SD[3:0] sampling edge.
serial interface timing slave (power up default),
AO_SCK acts as input. It receives the Serial
Clock from the external audio D/A subsystem.
The clock is treated as fully asynchronous to the
PNX1500 main clock.
interface timing master, AO_SCK acts as output.
It drives the Serial Clock for the external audio
D/A subsystem. The clock frequency is a
programmable integral divide of the AO_OSCLK
frequency.
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
series resistor is recommended to
series resistor is
s
over sampling clock by
© NXP B.V. 2007. All rights reserved.
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