PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 528

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
2. Functional Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
Audio In Block Diagram
AI_OSCLK
AI_SD[0]
AI_SCK
AI_SD[2]
AI_SD[3]
AI_SD[1]
AI_WS
Serial To Parallel Converter
SCK Divider
Clock Divider/Generator
WS Divider
The Audio In module has four major subsystems: a programmable sample clock
generator, a serial-to-parallel converter, a DTL initiator interface that initiates transfer
of parallel data to a DTL-to-memory bus adapter and a MMIO type low latency DTL
target interface for MMIO configuration registers.
The sampling clock can be used as either master or slave to the external A/D device.
The sampling clock synchronizes the serial-to-parallel converter with the source data
stream. The samples enter the serial-to-parallel converter, which reformats the data
for the initiator. The initiator streams the parallel data in to the DTL-to-memory bus
adapter. All the buffering of data is done in this adapter. The adapter also acts as the
DMA engine and bursts data to memory using the address provided by the initiator.
Since buffering of data is heavily dependent on system level latency issues, it is best
done in the adapter. Hence the buffer is not present in this block and instead will be in
the adapter and sized according to system requirements.
Serial
Clock
Shift Register
Shift Register
Shift Register
Shift Register
Rev. 4.0 — 03 December 2007
Different Framing/Capture Options
Divider Value
Divider Value
Parallel Data
MMIO Registers Logic
DTL DMA Interface Logic
PNX15xx/952x Series
Chapter 16: Audio Input
© NXP B.V. 2007. All rights reserved.
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