PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 39

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 4: PNX1500 Interface
PNX15XX_PNX952X_SER_N_4
Product data sheet
Pin Name
AO_WS
AO_SD3
AO_SD2
AO_SD1
AO_SD0
SPDIF interface
SPDI
SPDO
10/100 LAN interface (MII)
LAN_CLK
LAN_TX_CLK/
LAN_REF_CLK
LAN_TX_EN
LAN_TXD3
LAN_TXD2
LAN_TXD1
LAN_TXD0
LAN_TX_ER
LAN_CRS/
LAN_CRS_DV
LAN_COL
BGA
Ball
AE20
AE19
AD13
AD14
AC15
AE14
AE13
AC24 BPT3MCHDT5V
AA23 BPT3MCHDT5V
AF21
AF20
AF19
AF22
AF18
AF14
AF15
A6
Pad
Type
BPT3MCHDT5V
BPX2T14MCP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS3CHP
BPTS1CP
BPTS3CP
Rev. 4.0 — 03 December 2007
I/O
Type
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
OUT
I/O
IN
IN
IN
IN
GPIO
#
21
25
24
23
22
56
57
35
39
38
37
36
40
41
42
-
-
P Description
U AO can operate in either master or slave mode.
U
U
U
U
D Input for SPDIF (Sony/Philips Digital Audio
U Output for SPDIF. Note that this low-impedance
U Clock to feed the external PHY, usually 50 MHz.
U MII Transmit clock or RMII reference clock. Both
D MII or RMII Transmit Enable
D
D
D
D
D MII Transmit Error
D MII Carrier Sense or RMII Carrier Sene and
D Collision Detect. This pin is 5 V tolerant input.
AO_WS is the word-select or frame-
synchronization signal from/to the external D/A
subsystem. Each audio channel receives 1 sample
for every WS period.
Serial Data to external audio D/A subsystem for first
2 of 8 channels. The timing of the transitions on
these outputs is determined by the CLOCK_EDGE
bit in the AO_SERIAL register, and can be on a
positive or negative AO_SCK edge.
Interface, a.k.a. Dolby Digital
audio data stream as per IEC958 with 1937
extensions. This pin is 5 V tolerant input.
driver requires a 27-33
PNX1500 to match the board line impedance. This
resistor becomes a part of the voltage divider
necessary to drive the IEC958 isolation
transformer.
LAN_TX_CLK and LAN_RX_CLK have to be
connected to the RMII reference clock in RMII
mode.
MII Transmit Data
MII Transmit Data
MII or RMII Transmit Data
MII or RMII Transmit Data
Receive Data Valid. This pin is 5 V tolerant input.
• When Audio-Out is programmed as the serial-
• When Audio Out is programmed as serial-
interface timing slave (power-up default),
AO_WS acts as an input. AO_WS is sampled on
the opposite AO_SCK edge at which
AO_SD[3:0] are asserted.
interface timing master, AO_WS acts as an
output. AO_WS is asserted on the same
AO_SCK edge as AO_SD[3:0].
PNX15xx/952x Series
Chapter 1: Integrated Circuit Data
resistor close to the
TM
), a self clocking
© NXP B.V. 2007. All rights reserved.
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