PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 354

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
DMA4
QVCP Top Level Diagram
DMA1
DMA2
DMA3
1.1 Features
Layer Structure
QVCP comprises various processing layers, a hierarchical mixer cascade (where an
image surface is always associated with a layer and a mixer structure), and an output
pipeline. A top-level block diagram is shown in
A layer contains various video and graphics processing functions (which are
necessary to accomplish the tasks mentioned above) and obtains data from a
particular data source. The data may provide a desktop image, a motion video image,
a cursor, or a sprite image. Registers in the layer select the data source and set the
display and the image-processing parameters.
A mixer is a functional block that selects between and manipulates data streams from
two sources: the pixel stream from its companion layer and the pixel stream output of
the previous mixer (in the hierarchy). The mixing functions include pixel inversion,
pixel selection (between sources), and alpha blending. The mixers operate on a per-
pixel basis using programmable logical raster operations (ROPs) to determine which
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Screen timing generation adopted to the connected display requirements (SD-TV
standards, HD-TV standards, progressive and interlaced formats)
Color space uniqueness of all the display surfaces
Merging of the image surfaces (blend, invert, exchange)
Positioning of the various surfaces (including finer positioning)
Brightness and contrast control on a per-surface basis
Gamma correction and noise shaping of the final composited image
Output format generation
VBI Data
Programming and Screen Timming Control
Rev. 4.0 — 03 December 2007
Layer1
Layer2
Mixer
Mixer_out
Figure
PNX15xx/952x Series
1.
Output Pipeline
Chapter 11: QVCP
© NXP B.V. 2007. All rights reserved.
11-354