PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 768

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 4: IIC Registers
Table 5: Status Codes
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x04 5008
31:8
7:3
2:0
Status
Code
STA
0x00
0x08
0x10
0x18
Symbol
Unused
STA
Unused
Bus/Module
Status
Bus Error
A Start condition
has been
transmitted
A repeated Start
condition has been
transmitted
SLA+W has been
transmitted; ACK
has been received
I2C STATUS REGISTER
When the CPU writes to DAT, the buffer is loaded with the contents of DAT(7) which is
the first bit to be transmitted to the SDA line. After nine serial clock pulses, the eight
bits in DAT will have been transmitted to the SDA line, and the acknowledge bit will be
present in ACK. Note that the eight transmitted bits are shifted back into DAT.
Bit [7:3]: STA Status register
STA is a read-only special function register. Writing to this register has no affect. The
three least significant bits are always zero. The bits 7-3 contain the status code.
There are 26 possible status codes. When STA contains 0xF8, no relevant state
information is available and no serial interrupt is requested. Reset initializes STA to
0xF8. All other STA values correspond to defined IIC module states.
See the last row of
Application Software Response
To/From DAT
No DAT Action 0
Load SLA+W
Load SLA+R
Load SLA+W
Load SLA+R
Load data byte 0
no DAT action
no DAT action
no DAT action
Acces
s
R
Value
-
0
-
Rev. 4.0 — 03 December 2007
To CON
STA
X
X
X
X
1
0
1
Table 5
Description
Ignore upon read. Write as zeroes.
Indicates the status of the IIC module.
Ignore upon read. Write as zeroes.
STO
1
0
0
0
0
0
0
1
1
for an explanation of the terms used.
SI
0
0
0
0
0
0
0
0
0
AA
X
X
X
X
X
X
X
X
X
Next Action Taken
HW will enter the “not addressed” slave
mode.
SLA+W will be transmitted, ACK bit will be
received (I
MST/TRX mode).
SLA+R will be transmitted, ACK bit will be
received (I
MST/REC mode).
SLA+W will be transmitted, ACK bit will be
received (I
MST/TRX mode).
SLA+R will be transmitted, ACK bit will be
received (I
MST/REC mode).
Data byte will be transmitted; ACK bit will be
received.
Repeat START will be transmitted
STOP condition will be transmitted; STOP
flag will be reset.
STOP condition followed by a START
condition will be transmitted; STO flag will
be reset.
PNX15xx/952x Series
2
2
2
2
C bus module will be switched to
C bus module will be switched to
C bus module will be switched to
C bus module will be switched to
Chapter 25: I
© NXP B.V. 2007. All rights reserved.
2
C Interface
25-768