PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 164

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 4:
Waveforms of the Blocking Logic
turn_off_ack
2.4 Bypass Clock Sources
turn_off
xtal_clk
clk_out
clk_pll
The blocking will be released after a safe interval of 300 s. The 300 s is counted
using the 27 MHz xtal_clk.
blocking lasts for less than 10 xtal_clk cycles since it assumes the clocks are stable.
Remark: That 2 blocking circuits are used so that xtal_clk may continue being output
uninterrupted while the PLL is being re-programmed
Clocks are also switched if:
In the event of any issue with the clock sources from the CAB, it is possible to switch
these clocks to off-chip sources. These external clock sources will be routed through
the GPIO pins as summarized in
operating mode but just a help for bringup systems based on PNX15xx/952x Series.
Table 8: Bypass Clock Sources
Clocks from Clock
Module
clk_tm
clk_mem
clk_2dde
clk_pci
clk_mbs
clk_tstamp
clk_lan
clk_iic
clk_dvdd
clk_dtl_mmio
•
•
the system has come out of reset and boot-up sequence
a clock needs to be stretched or stopped for DfD
Rev. 4.0 — 03 December 2007
clk_out blocked
300us
Bypass Control Register
CLK_TM_CTL
CLK_MEM_CTL
CLK_2DDE_CTL
CLK_PCI_CTL
CLK_MBS_CTL
CLK_TSTAMP_CTL
CLK_LAN_CTL
CLK_IIC_CTL
CLK_DVDD_CTL
CLK_DTL_MMIO_CTL
Figure 4
clk_out is blocked when
turn_off_ack=1. It is now
safe to re-program clk_pll
then release turn_off
Table
illustrates the sequence of events. The second
8. This mode is not meant to be a functional
PNX15xx/952x Series
(Section
Chapter 5: The Clock Module
2.6)
© NXP B.V. 2007. All rights reserved.
GPIO pin
Assignment
AI_WS
GPIO[7]
AI_SD[1]
AI_SD[2]
AI_SD[3]
AO_WS
AO_SD[0]
AO_SD[1]
AO_SD[2]
AO_SD[3]
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