PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 463

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 1:
Figure 2:
MMIO Bus
Top Level Block Diagram
DTL
Data
INITIATOR
DTL
Header
INITIATOR
FGPO Module Block Diagram
VDO Pads
32
DTL
MMIO
I/F
1.1 FGPO Overview
Figure 1
Busses within the PNX15xx/952x Series. All external FGPO signals are registered
and routed through the Output Router module before leaving the PNX15xx/952x
Series. Latency buffering of data and endian conversion is done in the MTL DTL
Adapter. All FGPO register access is through the MMIO DTL adapter.
Figure 2
Output Router
Clock Block
shows the top level connection of the FGPO module to the MMIO and MTL
shows the basic sections of the FGPO module.
DMA
ENGINE
32
Rev. 4.0 — 03 December 2007
fgpo_rec_sync
32
fgpo_buf_sync
Timestamp
FIFO
Chapter 13: FGPO: Fast General Purpose Output
32
32
PNX15xx/952x Series
Data
Output
Engine
8/16/32
© NXP B.V. 2007. All rights reserved.
64
fgpo_stop
fgpo_data
MTL Bus
fgpo_start
13-463