PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 753
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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4. Register Descriptions
PNX15XX_PNX952X_SER_N_4
Product data sheet
The actual interpretation of the contents of the MMIO registers is determined by a
software protocol used by the debug monitor running on the internal TM3260 CPU
and the debug front-end running on a host machine.
The communication between a host computer and a target system via JTAG requires
the following major components:
The PNX15xx/952x Series has two JTAG data registers and two JTAG control
registers (see
manipulate those registers.
control registers. The addresses are offsets from the MMIO_BASE.
Remark: The sleepless bit is not used in PNX15xx/952x Series.
1. A Host computer with a serial or parallel interface.
2. A JTAG interface module (hardware) that asynchronously transfers data to and
3. A JTAG controller on the PNX15xx/952x Series processor which provides a
The host computer transfers data to and from the JTAG interface module,
preferably in word-parallel fashion. Also needed is JTAG interface device driver
software to access and modify the registers of the JTAG interface module.
from the host computer.
The interface module synchronously transfers data to and from the JTAG TAP on
a PNX15xx/952x Series processor, supplies the test clock TCK and other signals
to the JTAG controller on PNX15xx/952x Series. The interface module may be a
PC plug-in board.
This module may transfer data from and to the host computer in bit-serial or
word-parallel fashion. It transfers data from and to the JTAG registers on the
PNX15xx/952x Series processor in bit-serial fashion in accordance with the IEEE
1149.1 Standard. The JTAG interface module connects to a 4 or 5-pin JTAG
connector on the PNX15xx/952x Series board which provides a path to the JTAG
pins on the PNX15xx/952x Series processor. It is the responsibility of the
interface module to scan data in and out of the PNX15xx/952x Series processor
into its internal buffers and make them available to the host computer.
bridge between the external JTAG TAP and the internal system.
The controller transfers data from/to the TAP to/from its scannable registers
asynchronous to the internal system clock. A monitor running on the internal
TM3260 CPU and the debugger front-end running on a host computer exchange
data via JTAG by reading/writing the MMIO registers reserved for this purpose,
including two control registers used for handshaking.
Figure
Rev. 4.0 — 03 December 2007
3) in MMIO space and a number of JTAG instructions to
Table 4
lists the MMIO addresses of the JTAG data and
PNX15xx/952x Series
Chapter 24: TM3260 Debug
© NXP B.V. 2007. All rights reserved.
24-753
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