PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 228

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
t
t
Figure 6:
H
L
DSACK
: DS_low * pci_clk period shown with DSACK monitoring
: DS_high * pci_clk period shown with DS_high = 1
pci_clk
ADDR
R/WN
DATA
frame
SEL
trdy
irdy
DS
AS
Motorola Write With DSACK
3.1.2 Motorola Style Interface
address
data1
The Motorola style interface supports 8-bit or 16-bit devices. The following timing
diagrams illustrate a 2-byte write and 2-byte read operation. The time between the
falling edge of AS and DS is controlled by the DS time high field in the profile register.
The time low is determined by the DS time low field of the profile register or by the
external device if “wait for ACK” is enabled.
The t
device according to the vendor’s specification. The resolution is a multiple of the PCI
clock period. Refer to the descriptions for the XIO Select Profile registers.
t
H
H
(write time high) and t
t
L
Rev. 4.0 — 03 December 2007
L
(wait low) timing should be programmed to match the
address + 1
data 2
PNX15xx/952x Series
Chapter 7: PCI-XIO Module
© NXP B.V. 2007. All rights reserved.
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