PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 547

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
2. Functional Description
3. Operation
PNX15XX_PNX952X_SER_N_4
Product data sheet
3.1.1 Sample Rate Programming
2.1 Architecture
2.2 General Operations
3.1 Clock Programming
The SPDO module has two basic components: a DMA engine and an emitter. The
emitter is clocked from the DDS (in the Clock module) and can be programmed to the
desired sample rare. The emitter delivers the data stream to the SPDIF Output pin.
Software initially gives SPDO two memory data buffers, then enables the SPDO
block. As soon as the first memory buffer is drained, SPDO requests a new buffer
from software while switching over the use the other memory buffer, and so on.
With the exception of the DDS operation, the SPDO block is generally software
compatible with that of the PNX1300 Series.
A programmable clock generated by the SPDO Direct Digital Synthesizer (DDS).
Note that the DDS resides in the central Clocks module.
In SPDIF, the frame rate always equals f
relation holds for PCM as well as for AC-3 and MPEG audio. Each frame consists of
128 Unit Intervals (UI’s). The length of a UI is determined by the frequency setting of
the SPDO Direct Digital Synthesizer (DDS) in the central clock module.
The DDS can be programmed to emit on chip frequencies from approximately. 1 Hz
to 80 MHz with a maximum jitter of less than 0.579 ns. Refer to
Module
Table 1
Table 1: SPDIF Out Sample Rates and Jitter
f s
f
32.000
44.100
48.000
96.000
s
=
(kHz)
---------------- -
f
128
DDS
shows settings for common sample rate and main clock values.
for details.
Rev. 4.0 — 03 December 2007
UI (nSec)
244.14
177.15
162.76
81.38
s
, the sample rate of embedded audio. This
PNX15xx/952x Series
Chapter 17: SPDIF Output
jitter (nSec)
0.579
0.579
0.579
0.579
Chapter 5 The Clock
© NXP B.V. 2007. All rights reserved.
17-547
(13)