PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 783

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 3: PMAN (Hub) Arbiter Registers
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
Offset 0x06 4200—423C Entries of Priority List (Set A)
Note: Offset 0x200 has the highest priority.
This register is identical to
Offset 0x06 4280—42BC Entries of Round Robin List #1 (Set A)
This register is identical to
Offset 0x06 4300—431C Entries of Round Robin List #2 (Set A)
This register is identical to
Arbiter Registers (Set B)
Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set B)
31:10
9:8
7:5
4:0
Offset 0x06 4600—463F Entries of Priority List (Set B)
Note: Offset 0x200 has the highest priority.
This register is identical to
Offset 0x06 4680—46BC Entries of Round Robin List #1 (Set B)
This register is identical to
Offset 0x06 4700—471C Entries of Round Robin List #2 (Set B)
This register is identical to
Offset 0x06 4800
Offset 0x06 4804
This register is identical to
31:28 Reserved
27:24 round_robin2_entries
23:21 Reserved
20:16 round_robin1_entries
15:13 Reserved
12:8
7:0
Symbol
Reserved
R/W Grant
Reserved
Agent_ID
priority_entries
TDMA_entries
Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set
Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set
Offset 0x06 4000—41FC Entries of TDMA Timing Wheel (Set
Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set
Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set
Offset 0x06 4400—45FC Entries of TDMA Timing Wheel (Set
Offset 0x06 4800 NR_ENTRIES_A (Set
NR_ENTRIES_A (Set A)
NR_ENTRIES_B (Set B)
Acces
s
R
R/W
R
R/W
R/W
R/W
R/W
R/W
R/W
R/W
R/W
…Continued
Value
0
0
0
0
0
0
0
0
0
0
0
Rev. 4.0 — 03 December 2007
Description
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Grant on read, write or both.
0x0 = grant independent whether it is a read or write
0x1, 0x2, 0x3 = reserved
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
ID of the agent that is identified by this entry.
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Number of valid entries in last round robin list #2
Programming any value > 8 will result in use of the full round-robin
list.
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Number of valid entries in first round robin list #1
Programming any value > 16 will result in use of the full round-robin
list.
To ensure software backward compatibility, writes to unused or
reserved bits should be zero and reads must be ignored.
Number of valid entries in priority list
Programming any value > 16 will result in use of full priority list.
Number of valid entries in TDMA wheel
Programming any value > 128 will result in use of all 128 entries.
A).
PNX15xx/952x Series
A).
A).
A).
B).
B).
B).
Chapter 26: Memory Arbiter
© NXP B.V. 2007. All rights reserved.
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