PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 670

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

1. Introduction
1.1 Features
The Ethernet Media Access Controller (LAN100) of the PNX15xx/952x Series
enables applications to receive and transmit data over an Ethernet link.
The LAN100 is a DMA-capable, 10/100 Mb/s Ethernet Media Access (MAC)
Controller. It connects to an external Ethernet Physical Layer (PHY) chip using a
standard Media Independent Interface (MII) or standard Reduced MII interface
(RMII).
The LAN100 provides the following functions:
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Chapter 23: LAN100 — Ethernet
Media Access Controller
PNX15xx/952x Series Data Book – Volume 1 of 1
Rev. 4.0 — 03 December 2007
Receives and transmits Ethernet packets via an external PHY chip
Connects to an external PHY chip via standard MII or standard Reduced MII
(RMII) interface
Implements the MAC sublayer of IEEE standard 802.3
Provides a flexible choice of FIFO buffers and on-chip host buses
DMA and FIFO managers with scatter/gather DMA and FIFO of frame
descriptors
Memory traffic is optimized by buffering and prefetching
Receive-packet filtering includes perfect address matching, hash table, imperfect
filtering, and four pattern-match filters.
Wake-on-LAN power management support allows system wake-up, using the
receive filters or a magic frame detection filter
Supports real-time traffic using time stamps
Contains dual transmit descriptor buffers, one for real-time traffic, one for
non-real-time traffic
Supports Quality-of-Service (QoS) using a low-priority and a high-priority
transmit queue
Provides VLAN support
Implements IEEE 802.3/clause 31 flow control for both receive and transmit.
Product data sheet