PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 328

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
3. Application Notes
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.5.5 Sequence of Actions
3.1 Memory Configurations
To enter halt mode, the DDR SDRAM Controller performs the following sequence of
actions:
To leave halt mode, the DDR controller performs the following action:
The DDR SDRAM Controller supports a wide range of DDR SDRAM memory
configurations. Some examples of memory configurations that are supported for an
external data bus of 32 bits are shown in
bank of DDR devices is connected to the DDR controller. Throughout this document
the term rank will be used for a physical bank in order to prevent any confusion with
the logical banks inside the DDR devices. On the right hand side of
ranks of DDR devices are connected to the DDR controller. In single rank
configurations, there is no need to drive the chip select inputs on the DDR devices
from the DDR controller. In a multi-rank configuration, each rank will receive its own
chip select signal from the DDR controller. The DDR controller offers a 1 to 1 match
with the pin names of the DDR memory devices.
1. Precharge all banks (of all ranks)
2. Apply a NOP command
3. Enter self refresh mode, with CKE low, deactivate internal DLL
•
256 DDR SDRAM Controller memory cycles with CKE high, NOP commands, to
activate DLL.
Rev. 4.0 — 03 December 2007
Figure
8. On the left side a single physical
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
Figure 8
two
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