PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 758
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
Specifications of PNX1500E
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1. Introduction
The PNX15xx/952x Series chip contains an I
variety of peripherals including consumer electronic appliances, video image
processing equipment, and miniature cards. The IIC module supports bi-directional
data transfer between master and slave in slow and fast speeds as well as multiple
master and slave modes. Arbitration between simultaneously transmitting masters
can be maintained without corruption of serial data on the bus. Serial clock
synchronization allows devices with different bit rates to communicate via one serial
bus, and it can be used as a handshake mechanism to suspend and resume serial
transfer. The IIC hardware architecture and software protocol is simple and versatile.
The on-chip IIC module provides a serial interface that meets the I
specification and supports all transfer modes to and from the I
following functionality:
The I
controlling the bus can be connected to it. Because more than one master could try to
initiate a data transfer at the same time, a collision detection scheme is used to
arbitrate between the multiple masters. If two or more masters attempt to transfer
information onto the bus, the first to produce a ‘one’ when the other produces a ‘zero’
will detect the collision and back off transferring information.
The clock signals during arbitration are a synchronized combination of the clocks
generated by the masters using the wired-AND connection to the SCL line. Two
wires, SDA serial data) and SCL (serial clock), carry information between the devices
connected to the I
Each device can operate as either a transmitter or receiver, depending on the
function of the device. In addition to transmitters and receivers, devices can also be
considered as masters or slaves when performing data transfers. A master is the
device which initiates a data transfer on the bus and generates the clock signals to
permit that transfer. Any device addressed by a master is considered a slave.
•
•
•
•
•
Chapter 25: I
PNX15xx/952x Series Data Book – Volume 1 of 1
Rev. 4.0 — 03 December 2007
Both normal and fast modes up to 400 kHz.
32-bit word access from the CPU; no buffering is supported.
Generation of interrupts on I
Four modes of operation: master transmitter and receiver, slave transmitter and
receiver.
STO bit and the actual addresses of the Special Function Registers (SFRs).
2
C bus is a multi-master bus. This means that more than one device capable of
2
C bus.
2
2
C Interface
C state change
2
C module which interfaces with a
2
Product data sheet
C bus. It supports the
2
C bus
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