PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 739

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
5.16 Huge Frames and Frame Length Checking
AUTO_DETECT_PAD_ENABLE (ADPEN), VLAN_PAD_ENABLE (VLPEN) and
PAD_CRC_ENABLE (PADEN) bits of the MAC2 configuration register as well as the
Override and Pad bits from the transmit descriptor Control word. CRC generation is
affected by the CRC_ENABLE (CRCE) and DELAYED_CRC (DCRC) bits of the
MAC2 configuration register and the Override and CRC bits from the transmit
descriptor Control word.
The effective pad enable (EPADEN) is equal to the PAD_CRC_ENABLE bit from the
MAC2 register if the Override bit in the descriptor is 0. If the Override bit is 1, then
EPADEN will be taken from the descriptor Pad bit. Likewise, the effective CRC enable
(ECRCE) equals CRCE if the Override bit is 0, otherwise it equal the CRC bit from
the descriptor.
If padding is required and enabled, a CRC will always be appended to the padded
frames. A CRC will only be appended to the non-padded frames if ECRCE is set.
If EPADEN is 0, the packet will not be padded, and no CRC will be added unless
ECRCE is set.
If EPADEN is 1, then small packets will be padded, and a CRC will always be added
to the padded frames. In this case, if ADPEN and VLPEN are both 0, then the packets
will be padded to 60 bytes, and a CRC will be added, creating 64-byte packets. If
VLPEN is 1, the packets will be padded to 64 bytes and a CRC will be added,
creating 68 bytes packets. If ADPEN is 1 while VLPEN is 0, VLAN packets will be
padded to 64 bytes, non-VLAN packets will be padded to 60 bytes, and a CRC will be
added to padded packets creating 64- or 68-byte padded packets.
In case CRC generation is enabled, CRC generation can be delayed by four bytes to
skip proprietary header information.
The HUGE_FRAME_ENABLE bit in the MAC2 configuration register can be set to 1
to enable transmission and reception of packets of any length. Huge frame
transmission can be enabled on a per-packet basis by setting the Override and Huge
bits in the transmit descriptor Control word.
When enabling huge frames, the LAN100 will not check frame lengths or report frame
length errors (RangeError and LengthError). If huge frames are enabled, the received
byte count in the RSV register may be invalid because the frame may exceed the
maximum size. However, the EntryLevel fields from the receive status arrays will be
valid.
The LAN100 will check frame lengths by comparing the length/type field of the packet
to the actual number of bytes in the packet, and report a LengthError by setting the
corresponding bit in the receive StatusInfo word.
The MAXF register in the LAN100 allows the device driver to specify the maximum
number of bytes in a frame. The LAN100 will compare the actual receive frame to the
MAXF value and report a RangeError in the receive StatusInfo word if the packet is
larger.
Rev. 4.0 — 03 December 2007
Chapter 23: LAN100 — Ethernet Media Access Controller
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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