PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 722

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
5.8.1 Overview
5.6 Transmission Retry
5.7 time-stamps
5.8 Transmission modes
If a packet collision occurs on the Ethernet, it usually takes place during the collision
window spanning the first 64 bytes of a packet. If collision is detected, the LAN100
will retry the transmission. For this reason, the first 64 bytes of a packet are buffered
by the LAN100 so that it can be used during the retry. A transmission retry within the
first 64 bytes in a packet is fully transparent to the application and device driver
software.
When a collision occurs outside of the 64-byte collision window, a LateCollision error
is triggered and the transmission is aborted. After a LateCollision error, the remaining
data in the transmit packet is discarded. The LAN100 sets the Error and LateCollision
bits in the packet’s status fields. The Tx(Rt)Error bit in the IntStatus register is set. If
the corresponding bit in the IntEnable register is set, the Tx(Rt)Error bit in the
IntStatus register will be propagated to the CPU. The device driver software should
catch the interrupt and take appropriate actions.
The RETRANSMISSION_MAXIMUM field of the CLRT register can be used to
configure the maximum number of retries before aborting the transmission.
The LAN100 has an internal Time-stamp Counter register, readable by software via
the GlobalTimeStamp register. After reset, the Time-stamp Counter is 0. Every clock
tick of the Time-stamp Clock, the value of the Time-stamp Counter is incremented by
1. After 2
The Time-stamp Counter is only reset by asserting a hard reset.
Since the time-stamp is 32 bits in length, the maximum time that can be counted is
(2
Time-stamp Clock this corresponds to a 42 second period. The actual frequency of
the Time-stamp Clock may depend upon the software stack. The maximum
frequency supported by the hardware is 200 MHz.
The value of the Time-stamp Counter is copied in the time-stamp field of the status
word returned with transmit and receive fragments and packets. The device driver is
able to determine the exact moment of transmission, reception and latencies using
the time-stamp from the status word and the actual time-stamp value in the
GlobalTimeStamp register.
The LAN100 hardware has two transmission datapaths: Tx and TxRt. These
transmission datapaths can be switched in two modes:
32
•
–1) * T
Real-time/non-real-time mode: In this mode, the TxRt transmission datapath
handles real-time transmissions, and the Tx datapath handles non-real-time
transmissions.
32
clk
–1 clock ticks, the counter wraps back to 0.
where T
Rev. 4.0 — 03 December 2007
clk
Chapter 23: LAN100 — Ethernet Media Access Controller
is the period of the Time-stamp Clock. For a 100 MHz
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
23-722