PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 340

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
Table 9: Register Description
PNX15XX_PNX952X_SER_N_4
Product data sheet
Bit
3:0
Offset 0x06 50D4
31:4
3:0
Timing Characteristics
Offset 0x06 5100
31:20
19:16
15:4
3:0
Offset 0x06 5104
31:4
3:0
Offset 0x06 5108
31:4
3:0
Offset 0x06 510C
31:4
3:0
Offset 0x06 5110
31:4
3:0
Offset 0x06 5114
31:4
3:0
Offset 0x06 511C
31:4
3:0
Symbol
ROW_WIDTH
Unused
COLUMN_WIDTH
Unused
TRCD_WR
Unused
TRCD_RD
Unused
TRC
Unused
TWTR
Unused
TWR
Unused
TRP
Unused
TRAS
Unused
TRRD
RANK1_COLUMN_WIDTH
DDR_TRCD
DDR_TRC
DDR_TWTR
DDR_TWR
DDR_TRP
DDR_TRAS
DDR_TRRD
Access Value
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
R
R/W
0xd
-
0xa
-
2
-
4
-
0xd
-
2
-
3
-
4
-
9
-
2
Rev. 4.0 — 03 December 2007
Description
Row dimension: 2^ROW_WIDTH rows. I.e., a value of 0xc specifies
2^12 = 4096 rows. Only the following values are supported:
0x8, 0x9, 0xa, 0xb, 0xc, and 0xd (supporting 256 up to 8192 rows).
These bits should be ignored when read, and written as 0’s.
Column dimension: 2^COLUMN_WIDTH columns (each column
has a width of 32 bit). I.e., a value of 0xa specifies 2^10 = 1024
columns of 32 bit each. Only the following values are supported:
0x8, 0x9, 0xa, and 0xb (supporting 256 up to 2048 columns).
These bits should be ignored when read, and written as 0s.
Minimum time between active and write command (RAS to CAS
delay). When the datasheet of the DDR memory does not specify a
value for this timing parameter, use the value as specified for TRCD.
Must be greater or equal than tRAP.
These bits should be ignored when read, and written as 0s.
Minimum time between active and read command (RAS to CAS
delay). When the datasheet of the DDR memory does not specify a
value for this timing parameter, use the value as specified for TRCD.
Must be greater or equal than tRAP.
These bits should be ignored when read, and written as 0’s.
Minimum time between two active commands to the same bank.
These bits should be ignored when read, and written as 0’s.
Write to read command delay
These bits should be ignored when read, and written as 0’s.
Write recovery time.
Must be greater or equal than tWR_A.
TWR+TRP must be greater or equal than tDAL.
These bits should be ignored when read, and written as 0’s.
Precharge command period.
TWR+TRP must be greater or equal than tDAL.
These bits should be ignored when read, and written as 0s.
Minimum delay from active to precharge.
These bits should be ignored when read, and written as 0’s.
Active bank a to active bank b command
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
9-340