PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 4
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PNX1500E
Manufacturer Part Number
PNX1500E
Description
Manufacturer
NXP Semiconductors
Datasheet
1.PNX1500E.pdf
(828 pages)
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Manufacturer
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Part Number:
PNX1500E
Manufacturer:
NORTEL
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NXP Semiconductors
Volume 1 of 1
10.
10.1
10.1.1
10.1.2
10.1.3
10.1.4
10.2
Chapter 3: System On Chip Resources
1.
2.
2.1
2.2
2.3
2.4
2.4.1
2.5
3.
3.1
3.2
3.3
4.
4.1
5.
5.1
5.2
Chapter 4: Reset
1.
2.
2.1
2.2
2.2.1
2.2.2
2.3
Chapter 5: The Clock Module
1.
2.
2.1
2.2
2.2.1
2.2.2
2.2.3
2.2.4
2.2.5
2.3
2.4
2.5
PNX15XX_PNX952X_SER_N_4
Product data sheet
Peripheral Interface
Introduction
System Memory Map
System Principles
System Endian Mode
System Semaphores
Introduction
Functional Description
Introduction
Functional Description
GPIO - General Purpose Software I/O and
Flexible Serial Interface
Software I/O
Timestamping
Event sequence monitoring and signal generation
102
GPIO pin reset value
IR Remote Control Receiver and Blaster
The PCI View
The CPU View
The DCS View Or The System View
The Programmable DCS Apertures
DCS DRAM Aperture Control MMIO Registers
114
Aperture Boundaries
Module ID
Powerdown bit
System Module MMIO registers
System Endian Mode MMIO registers
Semaphore Specification
Construction of a 12-bit ID
RESET_IN_N or POR_IN_N?
The watchdog Timer
The Non Interrupt Mode
The Interrupt Mode
The Software Reset
The Modules and their Clocks
Clock Sources for PNX15xx/952x Series
PLL Specification
The Clock Dividers
The DDS Clocks
DDS and PLL Assignment Summary
External Clocks
Clock Control Logic
Bypass Clock Sources
Power-up and Reset sequence
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
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. . . . . . . . . . . . . . . . . . . . . . 114
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. . . . . . . . . . . . . . . . . . . . . 164
101
. . . . . . . . . . . . . . . . . . . . 109
. . . . . . . . . . . . . . . . . . . . 116
. . . . . . . . . . . . . . . . . . . . 117
. . . . . . . . . . . . . . . . . . . 144
. . . . . . . . . . . . . . . . . . 117
. . . . . . . . . . . . . . . . . . 141
. . . . . . . . . . . . . . . . . . 151
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. . . . . . . . . . . . . 165
. . . . . . . . . . . . 116
. . . . . . . . . 113
. . . . . . . . 112
. . . . . . . . 161
Rev. 4.0 — 03 December 2007
. . . . . . . 117
. . . . . 103
. . . . . 157
. .
10.3
10.3.1
10.3.2
10.3.3
10.4
11.
12.
5.3
5.4
5.5
6.
6.1
6.2
6.3
6.3.1
7.
7.1
8.
8.1
9.
10.
11.
12.
2.4
3.
3.1
3.2
4.
5.
2.6
2.7
2.8
2.8.1
2.9
2.10
2.11
2.11.1
2.11.2
2.12
2.12.1
2.12.2
Endian Modes
System Debug
System Related Information for TM3260
Video Input and Output Routers
Miscellaneous
System Registers Map Summary
Simplified Internal Bus Infrastructure
MMIO Memory MAP
References
Timing Description
Register Definitions
References
PNX15xx/952x Series
PCI-2.2 & XIO-16 Bus Interface Unit
PCI Capabilities
Simple Peripheral Capabilities (‘XIO-8/16’)
IDE Drive Interface
10/100 Ethernet MAC
The Master Semaphore
Usage Notes
Semaphore MMIO Registers
Interrupts
Timers
System Parameters for TM3260
TM3260 System Parameters MMIO Registers
MMIO Registers for the Input/Output Video/Data
Router
Miscellaneous System MMIO registers
The External Software Reset
The Hardware Timing
The Software Timing
Clock Stretching
Clock Frequency Determination
Power Down
Wake-Up from Power Down
Clock Detection
VDO Clocks
GPIO Clocks
Setting GPIO[14:12]/GCLOCK[2:0] as Clock
Outputs
GPIO[6:4]/CLOCK[6:4] as Clock Outputs
Clock Block Diagrams
TM3260, DDR and QVCP clocks
Clock Dividers
125
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
170
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167
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. . . . . . . . . . . . . . . . . . . . . . . . . . . 106
. . . . . . . . . . . . . . . . . . . . . . . . . . . 134
. . . . . . . . . . . . . . . . . . . . . . . . . . . 173
Connected Media Processor
. . . . . . . . . . . . . . . . . . . . . . . . . . 103
. . . . . . . . . . . . . . . . . . . . . . . . . . 107
. . . . . . . . . . . . . . . . . . . . . . . . . . 168
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. . . . . . . . . . . . . . . . . . . . . . . 106
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. . . . . . . . . . . . . . . . . . . . 170
. . . . . . . . . . . . . . . . . . . 118
. . . . . . . . . . . . . . . 119
. . . . . . . . . . . . . . . 167
© NXP B.V. 2007. All rights reserved.
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. . 104
. . 138
120
124
-iv
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