PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 320

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.2.4 Pre-Emption
whenever a clock cycle is spent on a CPU DDR burst, even if the burst is not for free.
To account for this the CPU_RATIO should be set by the amount CPU_DECR lower
as compared to the static ratios approach.
The arbitration scheme can be further fine tuned by specifying when arbitration is
done. An MTL transaction is chopped up into one or more DDR bursts, as the arbiter
operates on DDR bursts. Typically, the arbitration is done on an MTL transaction
basis; i.e., once an MTL transaction has been selected by the arbitration scheme, all
of its DDR bursts are processed before a new MTL transaction is selected. This
approach tries to maximize bandwidth efficiency by exploiting locality assumed to be
present within an MTL transaction. However, it might increase the expected latency of
some MTL transactions.
When there is a CPU MTL transaction present while doing arbitration in an HRT
window (and no DMA MTL transaction present). The CPU MTL transaction is
selected by the arbiter. While the CPU transaction is being processed, a DMA MTL
transaction becomes present (in the HRT window). The CPU MTL transaction is
consuming HRT window bandwidth, while a DMA MTL transaction is waiting to be
selected by the arbiter. From an overall bandwidth point of view, finishing the CPU
MTL transaction to completion might be a good idea, but the programmed bandwidth
partitioning is not fully applied. To address this issue, the concept of MTL transaction
pre-emption is introduced.
MTL transaction pre-emption is programmable (via the MMIO register ARB_CTL) and
can be used to interrupt an ongoing MTL transaction—before it is completed—to
favor another MTL transaction. Pre-emption allows ongoing CPU MTL transactions to
be interrupted by a DMA MTL transaction while in the HRT_WINDOW, and allows
ongoing DMA MTL transactions to be interrupted by a CPU MTL transaction while in
the CPU_WINDOW. Interruption of an MTL transaction of the same type will never
happen. Any interruption will reduce the overall efficiency of the DDR Controller as it
disallows exploiting locality assumed to be present within a MTL transaction.
The pre-emption field supports three different pre-emption settings.
the CPU pre-emption field.
Table 1: CPU Preemption Field
Preemption Field
Value
0
1
2
3
Rev. 4.0 — 03 December 2007
Description
No preemption (once a CPU MTL command has started to enter the
DDR arbitration buffer, it will go completely into the DDR arbitration
buffer, uninterrupted by other (CPU or DMA) MTL commands).
Preempt a CPU MTL command as it starts to enter the DDR arbitration
buffer while currently active in the DMA window. The CPU MTL
command will only be interrupted by a DMA MTL command, not by
another CPU MTL command. Default value
Undefined
Preempt a CPU MTL command that is currently active in the DMA
window (independent of when it started to enter the DDR arbitration
buffer).The CPU MTL command will only be interrupted by a DMA MTL
command, not by another CPU MTL command.
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
Table 1
describes
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