PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 569

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
3.2.11 Interrupts
3.2.12 Event Timestamping
The SPDI_STATUS register contains status flags that indicate certain conditions that
may need the attention of the chip level controller. Each of these conditions can be
used as interrupt sources.
The SPDI_INTEN register is used to provide the capability to enable any of the
interrupt source bits in the SPDI_STATUS register. To enable one of the interrupts
shown in the SPDI_STATUS register, the programmer must set the corresponding
SPDI_INTEN bits for that interrupt source. For example, to allow an interrupt to be
passed to the chip level interrupt controller upon the occurrence of a parity error in
the incoming stream during capture, the user must write a logic ‘1’ to the
PERR_ENBL bit in SPDI_INTEN. To disable an interrupt source, write a logic ‘0’ to
the appropriate bit in SPDI_INTEN. The effect of writing a logic ‘0’ to an enable bit
while the particular interrupt is active is that the interrupt is unconditionally de-
asserted and disabled.
The status conditions in the SPDI_STATUS register will be ‘sticky’, meaning the
SPDI_STATUS bit will remain active until explicitly cleared by setting the
corresponding clear bit in the SPDI_INTCLR register. Using the same example
above, if the parity error bit PERR is enabled (SPDI_INTEN.PERR_ENBL = 1) and
the PERR interrupt is active currently, to clear the PERR bit and deactivate the
interrupt the user must write a logic ‘1’ to the PERR_CLR bit in the SPDI_INTCLR
register.
The SPDI_INTSET register is useful for software diagnostic generation of interrupts.
Setting any of these bits to logic ‘1’ will generate an interrupt to the chip level interrupt
controller. To use the SPDI_INTSET register to generate interrupts, the same enable
rule applies as outlined above.
For SPDIF Input, the hardware interrupt signal is “level triggered”. This means the
interrupt signal passed to the chip level interrupt controller will be logic ‘1’ when active
and will remain so until cleared explicitly by the system interrupt handler software.
SPDIF Input has no timestamping internal to the block. Instead, SPDIF Input exports
several event notification signals to the central timestamping function on chip, see
Chapter 8 General Purpose Input Output Pins
Chapter 3 System On Chip
timers and timestamp registers to provide event counts and event triggered
“snapshot” clock values. The event signal is a positive edge going pulse with positive
level duration greater than or equal to 160 ns.
The specific events that are exported to the central timestamp function are:
•
WS (Word strobe) - this event signals the arrival of a sample pair on the SPDIF
Input interface. The rising edge of the signal indicates the beginning of either the
B or M subframe. The logic “high” duration is as stated above.
Rev. 4.0 — 03 December 2007
Resources. The central timestamp function includes
and
PNX15xx/952x Series
Section 8.1 on page 3-135
Chapter 18: SPDIF Input
© NXP B.V. 2007. All rights reserved.
in
18-569