PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 807

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
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4. PNX15xx/952x Series Endian Mode Architecture Details
PNX15XX_PNX952X_SER_N_4
Product data sheet
4.1 Global Endian Mode
4.2 Module Control
The programmer’s view of the PNX15xx/952x Series endian architecture is as
follows:
The CPU and all the modules always operate in a single endian mode. This endian
mode is determined by the BIG_ENDIAN bit in the SYS_ENDIANMODE register of
the PNX15xx/952x Series Global register module. The value of this bit is set during
system boot and normally not changed afterward.
Remark: The TM32 CPU core endian mode is determined by a bit in its PCSW. This
is historically set by the “crt0.s” software module on the TM32 CPU core, which
initializes the PCSW. The PNX15xx/952x Series version of this software module is
responsible for reading the SYS_ENDIANMODE.BIG_ENDIAN bit value and
establishing the same TM32 CPU core endian mode as the rest of the system.
All the modules have Control and Status registers, accessed by CPU Programmed I/
O. In the PNX15xx/952x Series, all programmed I/O happens through Memory
Mapped I/O registers. A separate Device Control and Status Bus (DCS Bus) is used
for all MMIO programming. A CPU can access Device Control and Status registers by
using the correct MMIO address for a module register. In the PNX15xx/952x Series,
all module registers are 32 bits wide and may only be accessed through 32-bit load/
store operations.
A control/status register load/store always copies the 32 bits verbatim between a
CPU register and the module register. The module’s left-most msb (bit 31) ends up in
the CPU’s left-most msb (bit 31), and the module’s right-most lsb (bit 0) ends up in the
right-most CPU register bit. This happens regardless of system endian mode
settings.
MMIO load and store instructions always see the same bit layout of module MMIO
registers, regardless of endian mode. The field and bit layout is precisely as specified
in the module register table with bit 31 designating the msb and bit 0 the lsb.
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The CPU and the modules on the PNX15xx/952x Series store and retrieve audio
samples, image pixels and data observing both the CPU rule and DMA rule.
The system as a whole runs in either little-endian or big-endian mode.
The mode is determined by the “BIG_ENDIAN” bit in the SYS_ENDIANMODE
register, see
which is “exported” to other modules.
The value of this bit is set during system initialization.
Rev. 4.0 — 03 December 2007
Chapter 3 System On Chip Resources Section 3.3 on page
PNX15xx/952x Series
Chapter 29: Endian Mode
© NXP B.V. 2007. All rights reserved.
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