PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 145

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 2:
SYS_RST_OUT_N
Watchdog_count
watchdog_reset
sys_rst_out_n
clk_dtl_mmio
Watchdog in Non Interrupt Mode
peri_rst_n
1: The watchdog count register is programmed
2: The count is happening
3: The count reaches the programmed value and a watchdog reset is issued
4: Both the internal and the external resets are asserted
2.2.2 The Interrupt Mode
0
The following
In this mode, the watchdog timer generates first an interrupt to the TM3260 before a
PNX15xx/952x Series system reset is generated (when a time-out occurs because
the TM3260 does not answer in time to the interrupt). The sequence of operations is
similar to the non interrupt mode.
First TM3260 CPU writes a value different than 0x0 to the WATCHDOG_COUNT
MMIO register. This starts an internal counter from the value 0x0. When the internal
counter reaches the WATCHDOG_COUNT value an interrupt, SOURCE 42 (see
Section 6.2 on page
started. If this second counter reaches the value previously stored into the
INTERRUPT_COUNT MMIO register then a PNX15xx/952x Series system reset is
asserted. The reset follows then the regular software reset timing,
TM3260 CPU clears the pending interrupt by writing to the INTERRUPT_CLEAR
MMIO register, then the PNX15xx/952x Series system reset is not generated.
The following summarizes the sequence of operations
Remark: A write of any nonzero value other than the current value will reset the count.
However this is not intended to be used as such.
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1. Enable the watchdog interrupt. This includes proper set-up of TM3260 internal
2. Initialize the INTERRUPT_COUNT MMIO register with the maximum interrupt
3. Start the first counter by writing a nonzero value to the WATCHDOG_COUNT
4. A write with 0x0 value to the WATCHDOG_COUNT MMIO register will stop the
interrupt controller[1] as well as an enable of the INTERRUPT_ENABLE MMIO
register.
latency authorized before a PNX15xx/952x Series reset is asserted.
MMIO register.
count. However this is not intended to be used as such.
1
2
Figure 2
Rev. 4.0 — 03 December 2007
3
3-122) is asserted. From here a second internal counter is
pictures the events.
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5
2
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FD
FE
PNX15xx/952x Series
FF
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Section
© NXP B.V. 2007. All rights reserved.
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Chapter 4: Reset
4
3.2. If the
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