PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 473

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
Figure 5:
must be low 1 clock
cycle before going active
must be high 1 clock
cycle before going active
Signal Edge Definition
clk
clk
3.1.2 Interrupt Service Routines
3.1.3 Optimized DMA Transfers
3.1.4 Terminating DMA Transfers
3.1.5 Signal Edge Definitions
Software must update the FGPO_BASEn register value (where n is the number of the
buffer that interrupted with a buffer done interrupt) BEFORE clearing the buffer done
interrupt flag. This must be done even if the base address of the buffer does not
change.
The DDR Memory controller used in the PNX15xx/952x Series is optimized for 128-
byte block transfers on 128-byte address boundaries. To keep Main Memory bus
traffic at a minimum the programmer should program the FGPO_BASE1 and
FGPO_BASE2 with bits [6:0] = 0000000 and program the FGPO_STRIDE to
multiples of 128.
During the next-to-last BUFnDONE interrupt service routine turn off (set to ‘0’) the
associated FGPO_CTL.OUTPUT_ENABLE_n bit.
During the last BUFnDONE interrupt service routine turn off (set to ‘0’) the associated
FGPO_CTL.OUTPUT_ENABLE_n bit, the FGPO is now IDLE
The FGPO uses only the rising edge of clk_fgpo. If the negative edge of an external
clock needs to be used, program the PNX15xx/952x Series clock module to invert the
external clock for the FGPO.
(for pins: fgpo_start, fgpo_rec_start, fgpo_stop, fgpo_buf_start)
sample point
sample point
Rev. 4.0 — 03 December 2007
RISING EDGE
FALLING EDGE
Chapter 13: FGPO: Fast General Purpose Output
PNX15xx/952x Series
© NXP B.V. 2007. All rights reserved.
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