PNX1500E NXP Semiconductors, PNX1500E Datasheet - Page 321

• Manufacturer Part Number: PNX1500E
• Manufacturer: NXP Semiconductors

Specifications of PNX1500E

• Lead Free Status / Rohs Status: Not Compliant

NXP Semiconductors
Volume 1 of 1
PNX15XX_PNX952X_SER_N_4
Product data sheet
2.2.5 Back Log Buffer (BLB)
2.2.6 PMAN (Hub) versus DDR Controller Interaction
The request for a DDR burst that wins the arbitration is always put in a FIFO queue.
This FIFO is 5 levels deep to allow the DDR to look ahead and open and close pages
in memory banks in order to increase DDR efficiency. Unfortunately this also means
that a new high priority request that has immediately won the arbitration could
possibly wait 5 full DDR bursts before it gets serviced. In a system in which almost all
the available bandwidth is used (the FIFO is almost always full) this can significantly
increase the latency.
Usually CPU traffic requires low latency and DMA traffic requires high bandwidth. In
order to reduce latency for the CPUs, the back log buffer (BLB) has been
implemented. When the BLB is enabled (through the ARB_CTL register), DMA DDR
bursts that are in the FIFO can be temporarily moved to the BLB.
This is done under the following conditions:
The BLB therefore allows the CPU transaction to overtake the DMA transaction
already in the FIFO. Since the DDR Controller may have already opened/closed
pages for the DMA DDR bursts, this feature will reduce the DDR efficiency.
As soon as DMA requests start winning the arbitration again, the DMA DDR bursts
from the BLB get a higher priority than DMA requests from the MTL ports. Only when
BLB is empty, DMA requests from the MTL ports can be serviced.
An additional factor that must be considered is the interaction of the Hub and the
DDR Controller. The DDR Controller command FIFO (pipeline) is 5 entries, however
the PMAN only allows 3 transactions to be outstanding. This means that the other two
FIFO stages can (and will be) occupied by transactions from one of the CPUs. This
can result in unexpected CPU bandwidth of up to 50%. This value is an extreme
worst-case; a more realistic number (assuming some kind of video decoding) is
around 15% of the gross DDR memory cycles.
Under the condition that the total required CPU budget is more than the maximum
“leakage” of bandwidth it is possible to reduce the additional “leakage” (above and
beyond budget) to zero by setting the value for CLIP = LIMIT + 2 * RATIO * <average
transaction latency>.
The net result of this setting is that although “leakage” will still occur, it will be charged
against the budget and compensated for immediately after occurrence.
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The FIFO entries hold a DMA DDR burst.
No DDR burst of the same DMA MTL transaction has reached the top of the FIFO
yet.
the BLB is empty
A CPU DDR burst request wins the arbitration.
CPU traffic has higher priority than DMA traffic. (This is important in case the
CPU wins arbitration, despite being lower priority than DMA, due only to the
absence of DMA traffic.)
Rev. 4.0 — 03 December 2007
PNX15xx/952x Series
Chapter 9: DDR Controller
© NXP B.V. 2007. All rights reserved.
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