HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 726

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Appendix A On-Chip Supporting Module Registers
Timer Status Register DL
(TSRDL)
Note:
Bit
7
6
5
4
Rev. 5.00 Jan 06, 2006 page 704 of 818
REJ09B0273-0500
Initial value:
* Only 0 can be written to clear the flag.
Bit name:
Bit Name
Overflow flag
(OVF4)
Input capture/
compare match
flag (IMF4D)
Input capture/
compare match
flag (IMF4C)
Input capture/
compare match
flag (IMF4B)
R/W:
Bit:
R/(W) *
OVF4
7
0
Value
0
1
0
1
0
1
0
1
R/(W) *
IMF4D
6
0
Description
[Clearing condition]
Read OVF4 when OVF4 =1, then write 0 in OVF4
[Setting condition]
TCNT4 overflowed from H'FFFF to H'0000
[Clearing condition]
Read IMF4D when IMF4D =1, then write 0 in IMF4D
[Setting conditions]
1. TCNT4 value is transferred to GR4D by an input capture
2. TCNT4 = GR4D when GR4D functions as an output
[Clearing condition]
Read IMF4C when IMF4C =1, then write 0 in IMF4C
[Setting conditions]
1. TCNT4 value is transferred to GR4C by an input capture
2. TCNT4 = GR4C when GR4C functions as an output
[Clearing condition]
Read IMF4B when IMF4B =1, then write 0 in IMF4B
[Setting conditions]
1. TCNT4 value is transferred to GR4B by an input capture
2. TCNT4 = GR4B when GR4B functions as an output
R/(W) *
IMF4C
signal when GR4D functions as an input capture register
compare register
signal when GR4C functions as an input capture register
compare register
signal when GR4B functions as an input capture register
compare register
5
0
H'FFFF8205
(Channels 3 to 5)
R/(W) *
IMF4B
4
0
R/(W) *
IMF4A
3
0
R/(W) *
OVF5
2
0
8
R/(W) *
IMF5B
1
0
(Initial value)
(Initial value)
(Initial value)
(Initial value)
R/(W) *
IMF5A
ATU
0
0