HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 150

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 8 Bus State Controller (BSC)
8.4
When a read from a slow device is completed, data buffers may not go off in time to prevent data
conflicts with the next access. If there is a data conflict during memory access, the problem can be
solved by inserting a wait in the access cycle.
To enable detection of bus cycle starts, waits can be inserted between access cycles during
continuous accesses of the same CS space by negating the CSn signal once.
8.4.1
For the two cases of write cycles after read cycles, and read cycles for a different area after read
cycles, waits are inserted so that the number of idle cycles specified by the IW31 to IW00 bits of
the BCR2 and the DIW of the DCR occur. When idle cycles already exist between access cycles,
only the number of empty cycles remaining beyond the specified number of idle cycles are
inserted.
Figure 8.7 shows an example of idles between cycles. In this example, 1 idle between CSn space
cycles has been specified, so when a CSm space write immediately follows a CSn space read
cycle, 1 idle cycle is inserted.
Rev. 5.00 Jan 06, 2006 page 128 of 818
REJ09B0273-0500
Waits between Access Cycles
Prevention of Data Bus Conflicts