HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 464

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 14 A/D Converter
14.2.3
A/D control register 0 (ADCR0) is an 8-bit readable/writable register that controls the start of A/D
conversion and selects the operating clock.
ADCR0 is initialized to H'1F by a power-on reset, and in hardware standby mode and software
standby mode.
Bits 4 to 0 of ADCR0 are reserved. These bits cannot be written to, and always return 1 if read.
Bit 7—Trigger Enable (TRGE): Enables or disables triggering of A/D conversion by external
input or the ATU.
Bit 7:
TRGE
0
1
For details of external or ATU trigger selection, see section 14.2.6, A/D Trigger Register.
When ATU triggering is selected, clear bit 7 of the ADTRGR register to 0.
When external triggering is selected, upon input of a low-level pulse to the ADTRG pin after
TRGE has been set to 1, the A/D converter detects the falling edge of the pulse, and sets the
ADST bit to 1 in ADCR. The same operation is subsequently performed when 1 is written in the
ADST bit by software. External triggering of A/D conversion is only enabled when the ADST bit
is cleared to 0.
When external triggering is used, the low-level pulse input to the ADTRG pin must be at least 1.5
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clock cycles in width. For details, see section 14.4.4, External Triggering of A/D Conversion.
Initial value:
A/D Control Register 0 (ADCR0)
Description
A/D conversion triggering by external input or ATU is disabled
A/D conversion triggering by external input or ATU is enabled
R/W:
Bit:
TRGE
R/W
7
0
CKS
R/W
6
0
ADST
R/W
5
0
—
R
4
1
—
R
3
1
—
R
2
1
—
R
1
1
(Initial value)
—
R
0
1