HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 379

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

12.1.4
Table 12.2 summarizes the three WDT registers. They are used to select the clock, switch the
WDT mode, and control the reset signal.
Table 12.2 WDT Registers
Notes: In register access, three cycles are required for both byte access and word access.
12.2
12.2.1
The TCNT is an 8-bit read/write upcounter. (The TCNT differs from other registers in that it is
more difficult to write to. See section 12.2.4, Register Access, for details.) When the timer enable
bit (TME) in the timer control/status register (TCSR) is set to 1, the watchdog timer counter starts
counting pulses of an internal clock selected by clock select bits 2 to 0 (CKS2 to CKS0) in the
TCSR. When the value of the TCNT overflows (changes from H'FF to H'00), a watchdog timer
overflow signal (WDTOVF) or interval timer interrupt (ITI) is generated, depending on the mode
selected in the WT/IT bit of the TCSR.
The TCNT is initialized to H'00 by a power-on reset and when the TME bit is cleared to 0. It is not
initialized in the standby mode.
Name
Timer control/status
register
Timer counter
Reset control/status
register
Initial value:
1. Write by word transfer. It cannot be written in byte or longword.
2. Read by byte transfer. It cannot be read in word or longword.
3. Only 0 can be written in bit 7 to clear the flag.
Register Configuration
Register Descriptions
Timer Counter (TCNT)
R/W:
Bit:
Abbreviation R/W
TCSR
TCNT
RSTCSR
R/W
7
0
R/W
6
0
R/(W) *
R/W
R/(W) *
R/W
5
0
3
3
Initial Value
H'18
H'00
H'1F
R/W
4
0
Rev. 5.00 Jan 06, 2006 page 357 of 818
R/W
Section 12 Watchdog Timer (WDT)
3
0
Write *
H'FFFF8610
H'FFFF8612
R/W
1
2
0
Address
REJ09B0273-0500
R/W
Read *
H'FFFF8610
H'FFFF8611
H'FFFF8613
1
0
2
R/W
0
0