HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 667
HD64F7051SFJ20V
Manufacturer Part Number
HD64F7051SFJ20V
Description
MCU 5V 256K J-TEMP PB-FREE QFP-1
Manufacturer
Renesas Electronics America
Series
SuperH® SH7050r
Datasheet
1.HD64F7050SFJ20V.pdf
(843 pages)
Specifications of HD64F7051SFJ20V
Core Processor
SH-2
Core Size
32-Bit
Speed
20MHz
Connectivity
EBI/EMI, SCI
Peripherals
DMA, WDT
Number Of I /o
102
Program Memory Size
256KB (256K x 8)
Program Memory Type
FLASH
Ram Size
10K x 8
Voltage - Supply (vcc/vdd)
4.5 V ~ 5.5 V
Data Converters
A/D 16x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
168-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS
Quantity:
101
Part Number:
HD64F7051SFJ20V
Manufacturer:
RENESAS/瑞萨
Quantity:
20 000
- Current page: 667 of 843
- Download datasheet (5Mb)
21.2.2
The system control register (SYSCR) is an 8-bit readable/writable register that enables or disables
accesses to the on-chip RAM.
SYSCR is initialized to H'01 by the rising edge of a power-on reset.
Bits 7 to 1—Reserved: These bits are always read as 0, and should only be written with 0.
Bit 0—RAME Enable (RAME): Selects enabling or disabling of the on-chip RAM. When
RAME is set to 1, on-chip RAM is enabled. When RAME is cleared to 0, on-chip RAM cannot be
accessed. In this case, a read or instruction fetch from on-chip RAM will return an undefined
value, and a write to on-chip RAM will be ignored. The initial value of RAME is 1.
When on-chip RAM is disabled by clearing RAME to 0, do not place an instruction that attempts
to access on-chip RAM immediately after the SYSCR write instruction, as normal access cannot
be guaranteed in this case.
When on-chip RAM is enabled by setting RAME to 1, place an SYSCR read instruction
immediately after the SYSCR write instruction. Normal access cannot be guaranteed if an on-chip
RAM access instruction is placed immediately after the SYSCR write instruction.
Bit 0: RAME
0
1
Initial value:
System Control Register (SYSCR)
R/W:
Bit:
Description
On-chip RAM disabled
On-chip RAM enabled (initial value)
—
R
7
0
—
R
6
0
—
R
5
0
—
R
4
0
Rev. 5.00 Jan 06, 2006 page 645 of 818
—
R
3
0
Section 21 Power-Down State
—
R
2
0
REJ09B0273-0500
—
R
1
0
RAME
R/W
0
1
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