HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 397

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

13.2.5
The serial mode register (SMR) is an 8-bit register that specifies the SCI serial communication
format and selects the clock source for the baud rate generator.
The CPU can always read and write the SMR. The SMR is initialized to H'00 by a power-on reset,
in hardware standby mode and software standby mode.
Bit 7—Communication Mode (C/A A A A ): Selects whether the SCI operates in the asynchronous or
clock synchronous mode.
Bit 6—Character Length (CHR): Selects 7-bit or 8-bit data in the asynchronous mode. In the
clock synchronous mode, the data length is always eight bits, regardless of the CHR setting.
Bit 5—Parity Enable (PE): Selects whether to add a parity bit to transmit data and to check the
parity of receive data, in the asynchronous mode. In the clock synchronous mode, a parity bit is
neither added nor checked, regardless of the PE setting.
Bit 7: C/A A A A
0
1
Bit 6: CHR
0
1
Bit 5: PE
0
1
Initial value:
Serial Mode Register (SMR)
R/W:
Bit:
R/W
C/A
7
0
Description
Asynchronous mode (initial value)
Clocked synchronous mode
Description
Eight-bit data (initial value)
Seven-bit data. (When 7-bit data is selected, the MSB (bit 7) of the
transmit data register is not transmitted.)
Description
Parity bit not added or checked (initial value)
Parity bit added and checked. When PE is set to 1, an even or odd
parity bit is added to transmit data, depending on the parity mode (O/E)
setting. Receive data parity is checked according to the even/odd (O/E)
mode setting.
CHR
R/W
6
0
R/W
PE
5
0
Section 13 Serial Communication Interface (SCI)
R/W
O/E
4
0
Rev. 5.00 Jan 06, 2006 page 375 of 818
STOP
R/W
3
0
R/W
MP
2
0
REJ09B0273-0500
CKS1
R/W
1
0
CKS0
R/W
0
0