HD64F7051SFJ20V Renesas Electronics America, HD64F7051SFJ20V Datasheet - Page 578

• Manufacturer Part Number: HD64F7051SFJ20V
• Description: MCU 5V 256K J-TEMP PB-FREE QFP-1
• Manufacturer: Renesas Electronics America
• Series: SuperH® SH7050r

Specifications of HD64F7051SFJ20V

• Core Processor: SH-2
• Core Size: 32-Bit
• Speed: 20MHz
• Connectivity: EBI/EMI, SCI
• Peripherals: DMA, WDT
• Number Of I /o: 102
• Program Memory Size: 256KB (256K x 8)
• Program Memory Type: FLASH
• Ram Size: 10K x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 168-QFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -

Section 18 ROM (128 kB Version)
18.7
A software method, using the CPU, is employed to program and erase flash memory in the on-
board programming modes. There are four flash memory operating modes: program mode, erase
mode, program-verify mode, and erase-verify mode. Transitions to these modes can be made by
setting the PSU, ESU, P, E, PV, and EV bits in FLMCR1.
The flash memory cannot be read while being programmed or erased. Therefore, the program
(programming control program) that controls flash memory programming/erasing should be
located and executed in on-chip RAM or external memory.
Notes: 1. Operation is not guaranteed if setting/resetting of the SWE, ESU, PSU, EV, PV, E, and
18.7.1
Follow the procedure shown in the program/program-verify flowchart in figure 18.7 to write data
or programs to flash memory. Performing program operations according to this flowchart will
enable data or programs to be written to flash memory without subjecting the device to voltage
stress or sacrificing program data reliability. Programming should be carried out 32 bytes at a
time.
Following the elapse of 10 µs or more after the SWE bit is set to 1 in flash memory control
register 1 (FLMCR1), 32-byte program data is stored in the program data area and reprogram data
area, and the 32-byte data in the program data area in RAM is written consecutively to the
program address (the lower 8 bits of the first address written to must be H'00, H'20, H'40, H'60,
H'80, H'A0, H'C0, or H'E0). Thirty-two consecutive byte data transfers are performed. The
program address and program data are latched in the flash memory. A 32-byte data transfer must
be performed even if writing fewer than 32 bytes; in this case, H'FF data must be written to the
extra addresses.
Next, the watchdog timer is set to prevent overprogramming in the event of program runaway, etc.
Set 6.6 ms as the WDT overflow period. After this, preparation for program mode (program setup)
is carried out by setting the PSU bit in FLMCR1, and after the elapse of 50 µs or more, the
operating mode is switched to program mode by setting the P bit in FLMCR1. The time during
which the P bit is set is the flash memory programming time. Use a fixed 500 µs pulse for the
write time.
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REJ09B0273-0500
2. When programming or erasing, set FWE to 1 (programming/erasing will not be
3. Programming should be performed in the erased state. Do not perform additional
Programming/Erasing Flash Memory
Program Mode
P bits in FLMCR1 is executed by a program in flash memory.
executed if FWE = 0).
programming on previously programmed addresses.